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Searched refs:SET_BITFIELD (Results 1 – 10 of 10) sorted by relevance

/device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/
Dhal_pwm.c146 pwm[index]->LOAD01 = SET_BITFIELD(pwm[index]->LOAD01, PWM_LOAD01_0, load); in hal_pwm_enable()
147 pwm[index]->TOGGLE01 = SET_BITFIELD(pwm[index]->TOGGLE01, PWM_TOGGLE01_0, toggle); in hal_pwm_enable()
149 pwm[index]->LOAD01 = SET_BITFIELD(pwm[index]->LOAD01, PWM_LOAD01_1, load); in hal_pwm_enable()
150 pwm[index]->TOGGLE01 = SET_BITFIELD(pwm[index]->TOGGLE01, PWM_TOGGLE01_1, toggle); in hal_pwm_enable()
152 pwm[index]->LOAD23 = SET_BITFIELD(pwm[index]->LOAD23, PWM_LOAD23_2, load); in hal_pwm_enable()
153 pwm[index]->TOGGLE23 = SET_BITFIELD(pwm[index]->TOGGLE23, PWM_TOGGLE23_2, toggle); in hal_pwm_enable()
155 pwm[index]->LOAD23 = SET_BITFIELD(pwm[index]->LOAD23, PWM_LOAD23_3, load); in hal_pwm_enable()
156 pwm[index]->TOGGLE23 = SET_BITFIELD(pwm[index]->TOGGLE23, PWM_TOGGLE23_3, toggle); in hal_pwm_enable()
285 pwm[index]->ST1_23 = SET_BITFIELD(pwm[index]->ST1_23, REG_PWM2_ST1, st1); in hal_pwm_breathing_led_enable()
286 pwm[index]->TOGGLE23 = SET_BITFIELD(pwm[index]->TOGGLE23, PWM_TOGGLE23_2, st2); in hal_pwm_breathing_led_enable()
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Dhal_psram_v2.c441 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_DLL_RANGE, range); in hal_psram_phy_dll_config()
458 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_LDO_IEN1, 0xd); in hal_psram_phy_init()
459 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_LDO_IEN2, 0x7); in hal_psram_phy_init()
460 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_LDO_VTUNE, 0x2); in hal_psram_phy_init()
462 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_LDO_RES, 0x4); in hal_psram_phy_init()
478 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_PSRAM_TXDRV, 0x3); in hal_psram_phy_init()
484 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_DLL_SWRC, 0x0); in hal_psram_phy_init()
536 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_LDO_IEN1, 0xd); in hal_psram_phy_wakeup()
537 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_LDO_IEN2, 0x7); in hal_psram_phy_wakeup()
538 val = SET_BITFIELD(val, PSRAM_ULP_PHY_REG_LDO_VTUNE, 0x2); in hal_psram_phy_wakeup()
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Dhal_dsi.c677 lcdc->REG_188 = SET_BITFIELD(lcdc->REG_188, LCD_CFG_SMPNVSYNC, 1); in hal_lcdc_init()
679 lcdc->REG_210 = SET_BITFIELD(lcdc->REG_210, LCD_CFG_EXTRA_DELAY, 4); in hal_lcdc_init()
776 lcdc->REG_188 = SET_BITFIELD(lcdc->REG_188, LCD_CFG_SMPNVSYNC, 3); in hal_lcdc_frame_done_irq_disable()
781 lcdc->REG_188 = SET_BITFIELD(lcdc->REG_188, LCD_CFG_SMPNVSYNC, 1); in hal_lcdc_frame_done_irq_enable()
Dplat_types.h103 #define SET_BITFIELD(reg, field, val) (((reg) & ~field ## _MASK) | BITFIELD_VAL(field, val)) macro
Dhal_dma.c933 …dma[inst]->_2D[hwch].SRC_INC = SET_BITFIELD(dma[inst]->_2D[hwch].SRC_INC, DMA_BURST_SRC_INC_VAL, i… in hal_dma_set_burst_addr_inc()
939 …dma[inst]->_2D[hwch].DST_INC = SET_BITFIELD(dma[inst]->_2D[hwch].DST_INC, DMA_BURST_DST_INC_VAL, i… in hal_dma_set_burst_addr_inc()
Dhal_spi.c338 ctrl->sspcr0_rx = SET_BITFIELD(ctrl->sspcr0_tx, SPI_SSPCR0_DSS, cfg->rx_frame_bits - 1); in hal_spi_init_ctrl()
341 ctrl->sspcr0_rx = SET_BITFIELD(ctrl->sspcr0_tx, SPI_SSPCR0_DSS, cfg->rx_bits - 1); in hal_spi_init_ctrl()
518 spi[id]->SSPCR1 = SET_BITFIELD(spi[id]->SSPCR1, SPI_SLAVE_ID, cs); in hal_spi_set_cs_id()
Dhal_uart.c149 …uart[id].base->UARTOVSAMP = SET_BITFIELD(uart[id].base->UARTOVSAMP, UARTOVSAMP_RATIO, (over_sample… in set_baud_rate()
150 uart[id].base->UARTOVSAMPST = SET_BITFIELD(uart[id].base->UARTOVSAMPST, UARTOVSAMPST_START, 1); in set_baud_rate()
/device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/best2003/
Dhal_cmu_best2003.c460 cmu->TIMER0_CLK = SET_BITFIELD(cmu->TIMER0_CLK, CMU_CFG_DIV_TIMER00, div); in hal_cmu_timer_set_div()
462 cmu->TIMER0_CLK = SET_BITFIELD(cmu->TIMER0_CLK, CMU_CFG_DIV_TIMER01, div); in hal_cmu_timer_set_div()
464 cmu->TIMER1_CLK = SET_BITFIELD(cmu->TIMER1_CLK, CMU_CFG_DIV_TIMER10, div); in hal_cmu_timer_set_div()
466 cmu->TIMER1_CLK = SET_BITFIELD(cmu->TIMER1_CLK, CMU_CFG_DIV_TIMER11, div); in hal_cmu_timer_set_div()
468 cmu->TIMER2_CLK = SET_BITFIELD(cmu->TIMER2_CLK, CMU_CFG_DIV_TIMER20, div); in hal_cmu_timer_set_div()
470 cmu->TIMER2_CLK = SET_BITFIELD(cmu->TIMER2_CLK, CMU_CFG_DIV_TIMER21, div); in hal_cmu_timer_set_div()
592 cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_CFG_DIV_SDMMC, div) | in hal_cmu_sdmmc_set_pll_div()
863 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0); in hal_cmu_dsi_clock_enable()
867 SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_DSI, 0x4); in hal_cmu_dsi_clock_enable()
878 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0); in hal_cmu_dsi_clock_enable_v2()
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Dhal_iomux_best2003.c656 iomux->REG_004 = SET_BITFIELD(iomux->REG_004, IOMUX_GPIO_P02_SEL, 6); in hal_iomux_set_function()
661 iomux->REG_004 = SET_BITFIELD(iomux->REG_004, IOMUX_GPIO_P03_SEL, 6); in hal_iomux_set_function()
666 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P20_SEL, 9); in hal_iomux_set_function()
671 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P21_SEL, 9); in hal_iomux_set_function()
790 iomux->REG_008 = SET_BITFIELD(iomux->REG_008, IOMUX_GPIO_P16_SEL, IOMUX_FUNC_VAL_GPIO); in hal_iomux_uart0_connected()
827 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P20_SEL, IOMUX_FUNC_VAL_GPIO); in hal_iomux_uart1_connected()
1850 val = SET_BITFIELD(val, IOMUX_GPIO_P00_SEL, 0xA); in hal_iomux_set_bt_rf_sw()
1854 val = SET_BITFIELD(val, IOMUX_GPIO_P01_SEL, 0xA); in hal_iomux_set_bt_rf_sw()
1966 iomux->REG_064 = SET_BITFIELD(iomux->REG_064, IOMUX_CFG_CODEC_TRIG_SEL, pin); in hal_iomux_set_codec_gpio_trigger()
/device/soc/goodix/gr551x/sdk_liteos/gr551x_sdk/components/libraries/utility/
Dutility.h159 #ifndef SET_BITFIELD
160 #define SET_BITFIELD(var, MSB, LSB, value) ((uint8_t)(var) = \ macro