1 /* 2 // Copyright (C) 2022 Beken Corporation 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_BASE_H__ 16 #define __REG_BASE_H__ 17 18 /*********************************************************************************************************************************** 19 * This file is generated from BK7256_ADDR Mapping_20211224_format_change_highlight_20220113_update.xlsm automatically 20 * Modify it manually is not recommended 21 * CHIP ID:BK7256,GENARATE TIME:2022-01-17 15:34:58 22 ************************************************************************************************************************************/ 23 24 #define SOC_SYSTEM_REG_BASE (0x44010000) 25 #define SOC_AON_PMU_REG_BASE (0x44000000) 26 #define SOC_CPU_PLIC_REG_BASE (0xE4000000) 27 #define SOC_AON_WDT_REG_BASE (0x44000600) 28 #define SOC_AON_GPIO_REG_BASE (0x44000400) 29 #define SOC_AON_RTC_REG_BASE (0x44000200) 30 #define SOC_FLASH_REG_BASE (0x44030000) 31 #define SOC_MBOX0_REG_BASE (0xA0000000) 32 #define SOC_MBOX1_REG_BASE (0xA0008000) 33 #define SOC_GENER_DMA_REG_BASE (0x44020000) 34 #define SOC_FFT_REG_BASE (0x47000000) 35 #define SOC_SBC_REG_BASE (0x47010000) 36 #define SOC_UART0_REG_BASE (0x44820000) 37 #define SOC_UART1_REG_BASE (0x45830000) 38 #define SOC_UART2_REG_BASE (0x45840000) 39 #define SOC_SPI_REG_BASE (0x44860000) 40 #define SOC_WDT_REG_BASE (0x44800000) 41 #define SOC_SPI1_REG_BASE (0x458C0000) 42 #define SOC_I2C0_REG_BASE (0x44850000) 43 #define SOC_I2C1_REG_BASE (0x45890000) 44 #define SOC_TIMER0_REG_BASE (0x44810000) 45 #define SOC_TIMER1_REG_BASE (0x45800000) 46 #define SOC_PWM01_REG_BASE (0x44840000) 47 #define SOC_PWM23_REG_BASE (0x44840040) 48 #define SOC_PWM45_REG_BASE (0x44840080) 49 #define SOC_SADC_REG_BASE (0x44870000) 50 #define SOC_EFUSE_REG_BASE (0x44880000) 51 #define SOC_IRDA_REG_BASE (0x44890000) 52 #define SOC_I2S_REG_BASE (0x47810000) 53 #define SOC_TRNG_REG_BASE (0x448A0000) 54 #define SOC_XVR_REG_BASE (0x4A800000) 55 #define SOC_AUD_REG_BASE (0x47800000) 56 #define SOC_LA_REG_BASE (0x45070000) 57 #define SOC_JPEG_REG_BASE (0x48000000) 58 #define SOC_JPEG_DEC_REG_BASE (0x48040000) 59 #define SOC_EIP130_REG_BASE (0x4b000000) 60 #define SOC_EIP130OTP_REG_BASE (0x4b004000) 61 #define SOC_EIP130REGITER_REG_BASE (0x4b008000) 62 #define SOC_QSPI_REG_BASE (0x46040000) 63 #define SOC_LCD_DISP_REG_BASE (0x48060000) 64 #define SOC_SDIO_REG_BASE (0x448B0000) 65 #define SOC_USB_REG_BASE (0x46002000) 66 #define SOC_RC_REG_BASE (0x4980C000) 67 #define SOC_TRX_REG_BASE (0x4980C200) 68 #define SOC_POWTBL_REG_BASE (0x4980C400) 69 #define SOC_DPDTBL_REG_BASE (0x4980C800) 70 #define SOC_AGCMEM_REG_BASE (0x4980A000) 71 #define SOC_PEAKCWMEM_REG_BASE (0x4980D000) 72 #define SOC_PSRAM_REG_BASE (0x46080000) 73 #endif //__REG_BASE_H__ 74