1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef __SOC_CAPS_H__ 16 #define __SOC_CAPS_H__ 17 18 /* 19 * Soc capabilities file, describing the following chip attributes: 20 * - Peripheral or feature supported or not 21 * - Number of resources (peripheral, channel, etc.) 22 * - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency 23 * supported, etc. 24 * 25 * For boolean definitions: 26 * - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`. 27 * (`#define` blank string causes error when checking by `#if x`) 28 * - if false: not define anything at all. 29 * (`#ifdef x` is true even when `#define 0` is defined before.) 30 * 31 * The code depending on this file uses these boolean definitions as `#if x` or `#if !x`. 32 * (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define 33 * x 0`, it's still a risk.) 34 * 35 * ECO & exceptions: 36 * For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by 37 * `#if x` and `#if !x`, making these missing definitions more obvious. 38 */ 39 #pragma once 40 41 #ifdef __has_include 42 # if __has_include("sdkconfig.h") 43 # include "sdkconfig.h" 44 # define SOC_CAPS_ECO_VER CONFIG_ESP32_REV_MIN 45 # endif 46 #endif 47 48 #if __DOXYGEN__ && !defined(SOC_CAPS_ECO_VER) 49 #define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX 50 #endif 51 52 #ifndef SOC_CAPS_ECO_VER 53 #warning ECO version not determined. Some ECO related caps will not be available. 54 #warning Define SOC_CAPS_ECO_VER before including this header. 55 56 // Define warning strings here for ECO-ed features to show error when they are used without being 57 // defined correctly 58 #define SOC_BROWNOUT_RESET_SUPPORTED "Not determined" 59 #define SOC_TWAI_BRP_DIV_SUPPORTED "Not determined" 60 #endif 61 62 /*-------------------------- COMMON CAPS ---------------------------------------*/ 63 #define SOC_CAPS_ECO_VER_MAX 3 64 65 #define SOC_MCPWM_SUPPORTED 1 66 #define SOC_SDMMC_HOST_SUPPORTED 1 67 #define SOC_BT_SUPPORTED 1 68 #define SOC_PCNT_SUPPORTED 1 69 #define SOC_SDIO_SLAVE_SUPPORTED 1 70 #define SOC_TWAI_SUPPORTED 1 71 #define SOC_EMAC_SUPPORTED 1 72 #define SOC_RISCV_COPROC_SUPPORTED 0 //TODO: correct the caller and remove this line 73 #define SOC_CPU_CORES_NUM 2 74 #define SOC_ULP_SUPPORTED 1 75 #define SOC_RTC_SLOW_MEM_SUPPORTED 1 76 #define SOC_CCOMP_TIMER_SUPPORTED 1 77 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1 78 79 /*-------------------------- ADC CAPS ----------------------------------------*/ 80 #define SOC_ADC_PERIPH_NUM (2) 81 #define SOC_ADC_PATT_LEN_MAX (16) 82 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (((PERIPH_NUM)==0)? 8: 10) 83 #define SOC_ADC_MAX_CHANNEL_NUM (10) 84 #define SOC_ADC_MAX_BITWIDTH (12) 85 86 /** 87 * Check if adc support digital controller (DMA) mode. 88 * @value 89 * - 1 : support; 90 * - 0 : not support; 91 */ 92 #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) (((PERIPH_NUM)==0)? 1: 0) 93 #define SOC_ADC_SUPPORT_RTC_CTRL 1 94 95 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ 96 #if SOC_CAPS_ECO_VER >= 1 97 #define SOC_BROWNOUT_RESET_SUPPORTED 1 98 #endif 99 100 /*-------------------------- CPU CAPS ----------------------------------------*/ 101 #define SOC_CPU_BREAKPOINTS_NUM 2 102 #define SOC_CPU_WATCHPOINTS_NUM 2 103 104 #define SOC_CPU_WATCHPOINT_SIZE 64 // bytes 105 106 /*-------------------------- DAC CAPS ----------------------------------------*/ 107 #define SOC_DAC_PERIPH_NUM 2 108 #define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit 109 110 /*-------------------------- GPIO CAPS ---------------------------------------*/ 111 // ESP32 has 1 GPIO peripheral 112 #define SOC_GPIO_PORT (1) 113 #define SOC_GPIO_PIN_COUNT 40 114 115 // SOC_GPIO_SUPPORT_RTC_INDEPENDENT not defined. On ESP32 those PADs which have RTC functions must 116 // set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to 117 // control pullup/down/capability, independent with RTC registers. 118 119 // 0~39 except from 20, 24, 28~31 are valid 120 #define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT20 | BIT24 | BIT28 | BIT29 | BIT30 | BIT31)) 121 // GPIO >= 34 are input only 122 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39)) 123 124 // Support to configure slept status 125 #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) 126 127 /*-------------------------- I2C CAPS ----------------------------------------*/ 128 // ESP32 have 2 I2C. 129 #define SOC_I2C_NUM (2) 130 131 #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ 132 133 #define SOC_I2C_SUPPORT_APB (1) 134 135 /*-------------------------- I2S CAPS ----------------------------------------*/ 136 // ESP32 have 2 I2S 137 #define SOC_I2S_NUM (2) 138 139 #define SOC_I2S_SUPPORTS_PDM (1) // ESP32 support PDM 140 #define SOC_I2S_SUPPORTS_ADC_DAC (1) // ESP32 support ADC and DAC 141 142 #define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated 143 144 #define SOC_I2S_APLL_MIN_FREQ (250000000) 145 #define SOC_I2S_APLL_MAX_FREQ (500000000) 146 #define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware 147 148 /*-------------------------- LEDC CAPS ---------------------------------------*/ 149 #define SOC_LEDC_SUPPORT_HS_MODE (1) 150 #define SOC_LEDC_SUPPORT_HS_MODE (1) 151 #define SOC_LEDC_CHANNEL_NUM (8) 152 #define SOC_LEDC_TIMER_BIT_WIDE_NUM (20) 153 154 /*-------------------------- MCPWM CAPS --------------------------------------*/ 155 #define SOC_MCPWM_PERIPH_NUM 2 ///< MCPWM peripheral number 156 #define SOC_MCPWM_TIMER_NUM 3 ///< Timer that each peripheral has 157 #define SOC_MCPWM_OP_NUM 3 ///< Operator that each peripheral has 158 #define SOC_MCPWM_COMPARATOR_NUM 2 ///< Comparator that each operator has 159 #define SOC_MCPWM_GENERATOR_NUM 2 ///< Generator that each operator has 160 #define SOC_MCPWM_FAULT_SIG_NUM 3 ///< Fault signal number that each peripheral has 161 162 /*-------------------------- MPU CAPS ----------------------------------------*/ 163 //TODO: correct the caller and remove unsupported lines 164 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 165 #define SOC_MPU_MIN_REGION_SIZE 0x20000000 166 #define SOC_MPU_REGIONS_MAX_NUM 8 167 #define SOC_MPU_REGION_RO_SUPPORTED 0 168 #define SOC_MPU_REGION_WO_SUPPORTED 0 169 170 /*-------------------------- PCNT CAPS ---------------------------------------*/ 171 // ESP32 have 1 PCNT peripheral 172 #define SOC_PCNT_PORT_NUM (1) 173 #define SOC_PCNT_UNIT_NUM (8) 174 #define SOC_PCNT_UNIT_CHANNEL_NUM (2) 175 176 /*-------------------------- RMT CAPS ----------------------------------------*/ 177 #define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */ 178 #define SOC_RMT_TX_CHANNELS_NUM (8) /*!< Number of channels that capable of Transmit */ 179 #define SOC_RMT_RX_CHANNELS_NUM (8) /*!< Number of channels that capable of Receive */ 180 #define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels (each channel can be configured to either TX or RX) */ 181 #define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ 182 #define SOC_RMT_SOURCE_CLK_INDEPENDENT (1) /*!< Can select different source clock for channels */ 183 184 /*-------------------------- RTCIO CAPS --------------------------------------*/ 185 #define SOC_RTCIO_PIN_COUNT 18 186 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 187 #define SOC_RTCIO_HOLD_SUPPORTED 1 188 #define SOC_RTCIO_WAKE_SUPPORTED 1 189 190 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/ 191 #define SOC_SIGMADELTA_NUM 1 192 #define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels 193 194 /*-------------------------- SPI CAPS ----------------------------------------*/ 195 #define SOC_SPI_PERIPH_NUM 3 196 #define SOC_SPI_DMA_CHAN_NUM 2 197 198 #define SOC_SPI_PERIPH_CS_NUM(i) 3 199 200 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 201 #define SOC_SPI_MAX_PRE_DIVIDER 8192 202 203 #define SOC_SPI_SUPPORT_AS_CS 1 //Support to toggle the CS while the clock toggles 204 205 // Peripheral supports DIO, DOUT, QIO, or QOUT 206 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)(spi_host); 1;}) 207 208 /*-------------------------- TIMER GROUP CAPS --------------------------------*/ 209 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64) 210 #define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16) 211 #define SOC_TIMER_GROUPS (2) 212 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2) 213 #define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) 214 #define SOC_TIMER_GROUP_LAYOUT {2,2} 215 216 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ 217 #define SOC_TOUCH_SENSOR_NUM (10) 218 219 #define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */ 220 #define SOC_TOUCH_PAD_THRESHOLD_MAX (0) /*!<If set touch threshold max value, The touch sensor can't be in touched status */ 221 #define SOC_TOUCH_PAD_WAKE_SUPPORTED (1) /*!<Supports waking up from touch pad trigger */ 222 223 /*-------------------------- TWAI CAPS ---------------------------------------*/ 224 #define SOC_TWAI_BRP_MIN 2 225 #if SOC_CAPS_ECO_VER >= 2 226 # define SOC_TWAI_BRP_MAX 256 227 # define SOC_TWAI_BRP_DIV_SUPPORTED 1 228 # define SOC_TWAI_BRP_DIV_THRESH 128 229 #else 230 # define SOC_TWAI_BRP_MAX 128 231 #endif 232 #define SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1 233 234 /*-------------------------- UART CAPS ---------------------------------------*/ 235 // ESP32 have 3 UART. 236 #define SOC_UART_NUM (3) 237 #define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */ 238 #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ 239 #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ 240 241 242 /*-------------------------- SPIRAM CAPS -------------------------------------*/ 243 #define SOC_SPIRAM_SUPPORTED 1 244 245 /*--------------------------- SHA CAPS ---------------------------------------*/ 246 /* ESP32 style SHA engine, where multiple states can be stored in parallel */ 247 #define SOC_SHA_SUPPORT_PARALLEL_ENG (1) 248 249 /* Supported HW algorithms */ 250 #define SOC_SHA_SUPPORT_SHA1 (1) 251 #define SOC_SHA_SUPPORT_SHA256 (1) 252 #define SOC_SHA_SUPPORT_SHA384 (1) 253 #define SOC_SHA_SUPPORT_SHA512 (1) 254 255 256 /*--------------------------- RSA CAPS ---------------------------------------*/ 257 #define SOC_RSA_MAX_BIT_LEN (4096) 258 259 260 /*-------------------------- AES CAPS -----------------------------------------*/ 261 #define SOC_AES_SUPPORT_AES_128 (1) 262 #define SOC_AES_SUPPORT_AES_192 (1) 263 #define SOC_AES_SUPPORT_AES_256 (1) 264 265 /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ 266 #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) 267 268 /*-------------------------- Power Management CAPS ---------------------------*/ 269 #define SOC_PM_SUPPORT_EXT_WAKEUP (1) 270 271 /* ---------------------------- Compatibility ------------------------------- */ 272 #define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED 273 #define CAN_BRP_MIN SOC_TWAI_BRP_MIN 274 #define CAN_BRP_MAX SOC_TWAI_BRP_MAX 275 #define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 276 #if SOC_CAPS_ECO_VER >= 2 277 # define CAN_BRP_DIV_SUPPORTED SOC_TWAI_BRP_DIV_SUPPORTED 278 # define CAN_BRP_DIV_THRESH SOC_TWAI_BRP_DIV_THRESH 279 #endif 280 281 /*------------------------------ BLE --------------------------------------------*/ 282 #define SOC_BLE_DONT_UPDATE_OWN_RPA (1) 283 284 #endif /* __SOC_CAPS_H__ */