Searched refs:SPI_FIFO_CTL_REG (Results 1 – 2 of 2) sorted by relevance
706 u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG); in spi_enable_dma_irq()710 writel(reg_val, base_addr + SPI_FIFO_CTL_REG); in spi_enable_dma_irq()718 u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG); in spi_disable_dma_irq()722 writel(reg_val, base_addr + SPI_FIFO_CTL_REG); in spi_disable_dma_irq()795 u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG); in spi_reset_fifo()801 writel(reg_val, base_addr + SPI_FIFO_CTL_REG); in spi_reset_fifo()806 u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG); in spi_set_rx_trig()810 writel(reg_val, base_addr + SPI_FIFO_CTL_REG); in spi_set_rx_trig()2455 SPI_FIFO_CTL_REG, readl(sspi->base_addr + SPI_FIFO_CTL_REG), in sunxi_spi_status_show()
43 #define SPI_FIFO_CTL_REG (0x18) /* fifo control register */ macro