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Searched refs:VMM_TO_DMA_ADDR (Results 1 – 12 of 12) sorted by relevance

/device/qemu/drivers/virtio/
Dvirtgpu.c210 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)req); in RequestResponse()
215 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)resp); in RequestResponse()
228 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)req); in RequestDataResponse()
233 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)data); in RequestDataResponse()
238 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)resp); in RequestDataResponse()
257 q->desc[head].pAddr = VMM_TO_DMA_ADDR((VADDR_T)req); in RequestNoResponse()
413 .addr = VMM_TO_DMA_ADDR(vaddr), in CMDResourceAttachBacking()
451 q->desc[i + 1].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&g_virtGpu->resp); in PopulateVirtQ()
703 info->memphys = (void *)VMM_TO_DMA_ADDR((VADDR_T)g_virtGpu->fb); in FbGetOverlayInfo()
742 VMM_TO_DMA_ADDR((VADDR_T)g_virtGpu->fb + (region->pgOff << PAGE_SHIFT)), in FbMmap()
Dvirtblock.c128 q->desc[i].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&blk->req); in PopulateRequestQ()
137 q->desc[i].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&blk->resp); in PopulateRequestQ()
151 q->desc[1].pAddr = VMM_TO_DMA_ADDR((VADDR_T)buf); in VirtblkIO()
Dvirtrng.c70 q->desc[0].pAddr = VMM_TO_DMA_ADDR((VADDR_T)buffer); in VirtrngIO()
Dvirtmmio.c132 addr = VMM_TO_DMA_ADDR(addr); in WriteQueueAddr()
Dvirtnet.c181 paddr = VMM_TO_DMA_ADDR((VADDR_T)nic->rbuf[i]); in PopulateRxBuffer()
244 trans->desc[head].pAddr = VMM_TO_DMA_ADDR((PADDR_T)&nic->vnHdr); in LowLevelOutput()
Dvirtinput.c116 q->desc[i].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&in->ev[i]); in PopulateEventQ()
/device/qemu/riscv32_virt/liteos_m/board/driver/
Dvirtgpu.c211 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req)); in RequestResponse()
216 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp)); in RequestResponse()
229 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req)); in RequestDataResponse()
234 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)data)); in RequestDataResponse()
239 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp)); in RequestDataResponse()
258 q->desc[head].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req)); in RequestNoResponse()
416 .addr = VMM_TO_DMA_ADDR(vaddr), in CMDResourceAttachBacking()
454 q->desc[i + 1].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)&g_virtGpu->resp)); in PopulateVirtQ()
717 info->memphys = (void *)VMM_TO_DMA_ADDR((VADDR_T)g_virtGpu->fb); in FbGetOverlayInfo()
Dvirtmmio.h29 #define VMM_TO_DMA_ADDR(vaddr) (vaddr) macro
Dvirtnet.c255 paddr = VMM_TO_DMA_ADDR(buf); in ConfigRxBuffer()
364 trans->desc[head].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((PADDR_T)&nic->vnHdr)); in LowLevelOutput()
371 trans->desc[tmp].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((PADDR_T)q->payload)); in LowLevelOutput()
Dvirtinput.c118 q->desc[i].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)&in->ev[i])); in PopulateEventQ()
/device/soc/hisilicon/common/platform/hieth-sf/src/
Dctrl.c368 HwXmitqPkg(ld, VMM_TO_DMA_ADDR(txqCur->txAddr), txqCur->tx.val); in HiethXmitGso()
411 …HiethWrite(ld, VMM_TO_DMA_ADDR((UINTPTR)NetBufGetAddress(netBuf, E_DATA_BUF)), UD_REG_NAME(GLB_IQ_… in HiethFeedHw()
/device/soc/hisilicon/common/platform/mmc/sdhci/
Dsdhci.c281 SdhciWritel(host, VMM_TO_DMA_ADDR((uintptr_t)host->admaDesc), (uintptr_t)ADMA_SA_LOW_R); in SdhciAdmaConfig()
357 SdhciDmaCacheClean((void*)VMM_TO_DMA_ADDR((uintptr_t)host->admaDesc), in SdhciAdmaTablePre()