1 /* 2 * Copyright (c) 2021 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 #ifndef HPM_ROMAPI_XPI_DEF_H 8 #define HPM_ROMAPI_XPI_DEF_H 9 10 /** 11 * @brief XPI ROM APIs 12 * @defgroup xpi_interface XPI driver APIs 13 * @{ 14 */ 15 16 #include "hpm_common.h" 17 18 /** 19 * @brief XPI_Type definitions for 20 * @note For compatibility 21 */ 22 typedef uint32_t XPI_Type; 23 24 /** 25 * @brief XPI Read Sample Clock source options 26 */ 27 typedef enum { 28 xpi_rxclksrc_internal_loopback = 0, /**< Internal loopback */ 29 xpi_rxclksrc_dqs_loopback = 1, /**< Loopback from DQS pad */ 30 xpi_rxclksrc_external_dqs = 3, /**< Read is driven by External DQS pad */ 31 } xpi_rxclksrc_type_t; 32 33 34 /** 35 * @brief XPI pad definitions 36 */ 37 #define XPI_1PAD (0U) /**< Single pad */ 38 #define XPI_2PADS (1U) /**< Dual pads */ 39 #define XPI_4PADS (2U) /**< Quad pads */ 40 #define XPI_8PADS (3U) /**< Octal pads */ 41 42 /** 43 * @brief XPI IO pin group options 44 */ 45 typedef enum { 46 xpi_io_1st_group, /**< First/Primary group */ 47 xpi_io_2nd_group, /**< Second/Secondary group */ 48 } xpi_io_group_t; 49 50 /** 51 * @brief XPI Transfer Channel type definitions 52 */ 53 typedef enum { 54 xpi_xfer_channel_a1, /**< The address is based on the device connected to Channel A1 */ 55 xpi_xfer_channel_a2, /**< The address is based on the device connected to Channel A2 */ 56 xpi_xfer_channel_b1, /**< The address is based on the device connected to Channel B1 */ 57 xpi_xfer_channel_b2, /**< The address is based on the device connected to Channel B2 */ 58 xpi_xfer_channel_auto, /**< The channel is auto determined */ 59 } xpi_xfer_channel_t; 60 61 /** 62 * @brief XPI Channel defitions 63 */ 64 typedef enum { 65 xpi_channel_a1, /**< Port: Channel A1 */ 66 xpi_channel_a2, /**< Port: Channel A2 */ 67 xpi_channel_b1, /**< Port: Channel B1 */ 68 xpi_channel_b2, /**< Port: Channel B2 */ 69 } xpi_channel_t; 70 71 /** 72 * @brief XPI APB Transfer type 73 */ 74 typedef enum { 75 xpi_apb_xfer_type_cmd, /**< APB Command Type: Command only */ 76 xpi_apb_xfer_type_config, /**< APB Command Type: Configuration */ 77 xpi_apb_xfer_type_read, /**< APB Command Type: Read */ 78 xpi_apb_xfer_type_write, /**< APB Command Type: Write */ 79 } xpi_apb_xfer_type_t; 80 81 /** 82 * @brief XPI Xfer Mode 83 */ 84 typedef enum { 85 xpi_xfer_mode_polling, /**< Transfer mode: Polling */ 86 xpi_xfer_mode_dma, /**< Transfer mode: DMA */ 87 xpi_xfer_mode_interrupt, /**< Transfer mode: Interrupt */ 88 } xpi_xfer_mode_t; 89 90 /** 91 * @brief XPI Xfer context 92 */ 93 typedef struct { 94 uint32_t addr; /**< device address for XPI transfer */ 95 uint8_t channel; /**< channel for XPI transfer */ 96 uint8_t cmd_type; /**< command type for XPI transfer */ 97 uint8_t seq_idx; /**< Sequence index for XPI transfer */ 98 uint8_t seq_num; /**< Sequence number for XPI transfer */ 99 uint32_t *buf; /**< Buffer for XPI transfer */ 100 uint32_t xfer_size; /**< Transfer size in bytes */ 101 } xpi_xfer_ctx_t; 102 103 /** 104 * @brief XPI instruction sequence 105 */ 106 typedef struct { 107 uint32_t entry[4]; 108 } xpi_instr_seq_t; 109 110 /** 111 * @brief XPI Phase definitions 112 */ 113 #define XPI_PHASE_STOP (0x00U) /**< Phase: Stop */ 114 #define XPI_PHASE_CMD_SDR (0x01U) /**< Phase: Send CMD in SDR mode */ 115 #define XPI_PHASE_RADDR_SDR (0x02U) /**< Phase: Send Row Address in SDR Mode */ 116 #define XPI_PHASE_CADDR_SDR (0x03U) /**< Phase: Send Column Address in SDR Mode */ 117 #define XPI_PHASE_MODE4_SDR (0x06U) /**< Phase: Send Mode 4 in SDR Mode */ 118 #define XPI_PHASE_MODE8_SDR (0x07U) /**< Phase: Send Mode 8 in SDR Mode */ 119 #define XPI_PHASE_WRITE_SDR (0x08U) /**< Phase: Write data in SDR Mode */ 120 #define XPI_PHASE_READ_SDR (0x09U) /**< Phase: Read data in SDR Mode */ 121 #define XPI_PHASE_DUMMY_SDR (0X0CU) /**< Phase: Send Dummy in SDR Mode */ 122 #define XPI_PHASE_DUMMY_RWDS_SDR (0x0DU) /**< Phase: Send Dummy RWDS in SDR Mode */ 123 124 #define XPI_PHASE_CMD_DDR (0x21U) /**< Phase: Send CMD in DDR Mode */ 125 #define XPI_PHASE_RADDR_DDR (0x22U) /**< Phase: Send Raw Address in DDR Mode */ 126 #define XPI_PHASE_CADDR_DDR (0x23U) /**< Phase: Send Column address in DDR Mode */ 127 #define XPI_PHASE_MODE4_DDR (0x26U) /**< Phase: Send Mode 4 in DDR Mode */ 128 #define XPI_PHASE_MODE8_DDR (0x27U) /**< Phase: Send Mode 8 in DDR Mode */ 129 #define XPI_PHASE_WRITE_DDR (0x28U) /**< Phase: Write data in DDR Mode */ 130 #define XPI_PHASE_READ_DDR (0x29U) /**< Phase: Read data in SDR Mode */ 131 #define XPI_PHASE_DUMMY_DDR (0x2CU) /**< Phase: Send DUMMY in DDR Mode */ 132 #define XPI_PHASE_DUMMY_RWDS_DDR (0x2DU) /**< Phase: Send DUMMY RWDS in DDR Mode */ 133 134 /** 135 * @brief XPI API command error codes 136 */ 137 enum { 138 status_xpi_apb_jump_on_cs = MAKE_STATUS(status_group_xpi, 1), 139 status_xpi_apb_unknown_inst = MAKE_STATUS(status_group_xpi, 2), 140 status_xpi_apb_dummy_sdr_in_ddr_seq = MAKE_STATUS(status_group_xpi, 3), 141 status_xpi_apb_dummy_ddr_in_sdr_seq = MAKE_STATUS(status_group_xpi, 4), 142 status_xpi_apb_exceed_addr_range = MAKE_STATUS(status_group_xpi, 5), 143 status_xpi_apb_seq_timeout = MAKE_STATUS(status_group_xpi, 6), 144 status_xpi_apb_cross_boundary = MAKE_STATUS(status_group_xpi, 7), 145 }; 146 147 /** 148 * @brief Delay line definitions 149 */ 150 enum { 151 xpi_dll_half_cycle = 0xFU, 152 xpi_dll_quarter_cycle = 0x7U, 153 xpi_dll_sdr_default_cycle = xpi_dll_half_cycle, 154 xpi_dll_ddr_default_cycle = xpi_dll_quarter_cycle, 155 }; 156 157 /** 158 * @brief XPI configuration structure 159 */ 160 typedef struct { 161 uint8_t rxclk_src; /**< Read sample clock source */ 162 uint8_t reserved0[7]; /**< Reserved */ 163 uint8_t tx_watermark_in_dwords; /**< Tx watermark in double words */ 164 uint8_t rx_watermark_in_dwords; /**< Rx watermark in double words */ 165 uint8_t enable_differential_clk; /**< Enable differential clock */ 166 uint8_t reserved1[5]; /**< Reserved */ 167 uint32_t access_flags; /**< Access flags */ 168 } xpi_config_t; 169 170 /** 171 * @brief XPI Device Configuration structure 172 */ 173 typedef struct { 174 uint32_t size_in_kbytes; /**< Device size in kbytes */ 175 uint32_t serial_root_clk_freq; /**< XPI serial root clock frequency */ 176 177 uint8_t enable_write_mask; /**< Enable write mask, typically for PSRAM/HyperRAM */ 178 uint8_t data_valid_time; /**< Data valid time, Unit 0.1ns */ 179 uint8_t reserved0[2]; 180 181 uint8_t cs_hold_time; /**< CS hold time, cycles in terms of FLASH clock */ 182 uint8_t cs_setup_time; /**< CS setup time, cycles in terms of FLASH clock */ 183 uint16_t cs_interval; /**< CS interval, cycles in terms of FLASH clock */ 184 185 uint8_t reserved1; 186 uint8_t column_addr_size; /**< Column address bits */ 187 uint8_t enable_word_address; /**< Enable word address, for HyperFLASH/HyperRAM */ 188 uint8_t dly_target; /**< Delay target */ 189 190 uint8_t ahb_write_seq_idx; /**< AHB write sequence index */ 191 uint8_t ahb_write_seq_num; /**< AHB write sequence number */ 192 uint8_t ahb_read_seq_idx; /**< AHB read sequence index */ 193 uint8_t ahb_read_seq_num; /**< AHB read sequence number */ 194 195 uint8_t ahb_write_wait_interval; /**< AHB write wait interval, in terms of FLASH clock */ 196 uint8_t reserved2[3]; 197 } xpi_device_config_t; 198 199 /** 200 * @brief SUB Instruction 201 * @param [in] phase Phase 202 * @param [in] pad Pad for Phase 203 * @param [in] op Operand for Phase 204 */ 205 #define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | ((uint16_t)(op)))) 206 /** 207 * @brief Generate a single word INSTRUCTION sequence word 208 * @note Here intentionally use the MACRO because when the arguments are constant value, the compiler 209 * can generate the const entry word during pre-processing 210 */ 211 #define XPI_INSTR_SEQ(phase0, pad0, op0, phase1, pad1, op1) (SUB_INSTR(phase0, pad0, op0) | (SUB_INSTR(phase1, pad1, op1)<<16)) 212 213 214 /** 215 * @} 216 */ 217 218 #endif /* HPM_ROMAPI_XPI_DEF_H */ 219