Searched refs:__R (Results 1 – 25 of 54) sorted by relevance
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15 __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */17 __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */18 __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */19 __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */20 …__R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and ta…21 __R uint32_t INFO; /* 0x1104: Version and the maximum priority */22 __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */25 __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */27 __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */31 __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */[all …]
15 __R uint8_t RESERVED0[972]; /* 0x34 - 0x3FF: Reserved */16 __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */17 __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */19 __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */22 __R uint32_t SEQ_WR_ADDR; /* 0x808: */25 __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */29 __R uint32_t PRD_RESULT; /* 0xC08: */30 __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */32 __R uint8_t RESERVED4[768]; /* 0xD00 - 0xFFF: Reserved */34 __R uint8_t RESERVED5[196]; /* 0x1040 - 0x1103: Reserved */[all …]
13 __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */15 __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */17 __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */
15 __R uint32_t STA; /* 0x8: Status Register */16 __R uint32_t ERR; /* 0xC: Error Registers */17 __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */18 __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */19 __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */
15 __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */16 __R uint32_t CNT; /* 0xC: Counter */17 __R uint8_t RESERVED1[16]; /* 0x10 - 0x1F: Reserved */
17 __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */21 __R uint8_t RESERVED1[16]; /* 0xE0 - 0xEF: Reserved */24 __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */25 __R uint32_t CAPPOS[24]; /* 0x100 - 0x15C: Capture rising edge register */26 __R uint8_t RESERVED3[16]; /* 0x160 - 0x16F: Reserved */27 __R uint32_t CNT; /* 0x170: Counter */28 __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */29 __R uint32_t CAPNEG[24]; /* 0x180 - 0x1DC: Capture falling edge register */30 __R uint8_t RESERVED5[16]; /* 0x1E0 - 0x1EF: Reserved */31 __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */[all …]
15 __R uint8_t RESERVED0[972]; /* 0x34 - 0x3FF: Reserved */16 __R uint32_t BUS_RESULT[19]; /* 0x400 - 0x448: */17 __R uint8_t RESERVED1[180]; /* 0x44C - 0x4FF: Reserved */19 __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */22 __R uint32_t SEQ_WR_ADDR; /* 0x808: */25 __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */29 __R uint32_t PRD_RESULT; /* 0xC08: */30 __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */32 __R uint8_t RESERVED4[720]; /* 0xD30 - 0xFFF: Reserved */34 __R uint8_t RESERVED5[184]; /* 0x104C - 0x1103: Reserved */[all …]
13 __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */16 __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */18 __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */27 __R uint32_t IIR; /* 0x28: Interrupt Identification Register */32 __R uint32_t LSR; /* 0x34: Line Status Register */33 __R uint32_t MSR; /* 0x38: Modem Status Register */
17 __R uint32_t RESP[4]; /* 0x10 - 0x1C: */19 __R uint32_t PSTATE; /* 0x24: */26 __R uint32_t CAPABILITIES1; /* 0x40: */27 __R uint32_t CAPABILITIES2; /* 0x44: */28 __R uint32_t CURR_CAPABILITIES1; /* 0x48: */29 __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */31 __R uint32_t ADMA_ERR_STAT; /* 0x54: */33 __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */34 __R uint16_t PRESET[11]; /* 0x60 - 0x74: */35 __R uint8_t RESERVED1[2]; /* 0x76 - 0x77: Reserved */[all …]
13 __R uint8_t RESERVED0[3072]; /* 0x0 - 0xBFF: Reserved */15 __R uint32_t STA; /* 0xC04: Status Register */16 __R uint8_t RESERVED1[248]; /* 0xC08 - 0xCFF: Reserved */26 __R uint8_t RESERVED0[32]; /* 0xD20 - 0xD3F: Reserved */
13 __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */14 __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */15 __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */18 __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */20 __R uint32_t CHEN; /* 0x34: Channel Enable Register */21 __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */
14 __R uint32_t RFIFO_FILLINGS; /* 0x4: Rx FIFO Filling Level */15 __R uint32_t TFIFO_FILLINGS; /* 0x8: Tx FIFO Filling Level */18 __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */19 __R uint32_t RXD[4]; /* 0x20 - 0x2C: Rx Data0 */21 __R uint8_t RESERVED1[16]; /* 0x40 - 0x4F: Reserved */23 __R uint8_t RESERVED2[4]; /* 0x54 - 0x57: Reserved */25 __R uint8_t RESERVED3[4]; /* 0x5C - 0x5F: Reserved */
18 __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */19 __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */20 __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */21 __R uint32_t CAPPRD; /* 0x28: PWM period measure register */22 __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */23 __R uint32_t CNT; /* 0x30: Counter */24 __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */26 __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */
19 __R uint8_t RESERVED0[12]; /* 0x18 - 0x23: Reserved */24 __R uint32_t W; /* 0x30: W counter */25 __R uint32_t V; /* 0x34: V counter */26 __R uint32_t U; /* 0x38: U counter */27 __R uint32_t TMR; /* 0x3C: Timer counter */30 __R uint32_t HIS0; /* 0x70: history register 0 */31 __R uint32_t HIS1; /* 0x74: history register 1 */
14 __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */21 __R uint8_t RESERVED0[12]; /* 0x94 - 0x9F: Reserved */22 __R uint32_t STATUS; /* 0xA0: PLLx status */23 __R uint8_t RESERVED1[28]; /* 0xA4 - 0xBF: Reserved */26 __R uint8_t RESERVED2[56]; /* 0xC8 - 0xFF: Reserved */
13 __R uint32_t T; /* 0x0: */14 __R uint32_t TMAX; /* 0x4: */15 __R uint32_t TMIN; /* 0x8: */16 __R uint32_t AGE; /* 0xC: */26 __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */
16 __R uint32_t TIMEH; /* 0x8: timestamp high */17 __R uint32_t TIMEL; /* 0xC: timestamp low */23 __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */25 __R uint32_t CAPT_SNAPH; /* 0x30: */27 __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */
14 __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */18 __R uint8_t RESERVED1[32]; /* 0x18 - 0x37: Reserved */25 __R uint8_t RESERVED2[64]; /* 0x50 - 0x8F: Reserved */31 __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */33 __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */34 __R uint32_t STAT0; /* 0xC0: Status Register 0 */35 __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */
15 __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */18 __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */23 __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */26 __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */28 __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */
14 __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */25 __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */27 __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */
13 __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */16 __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */22 __R uint32_t STATUS; /* 0x34: Status Register */26 __R uint8_t RESERVED2[28]; /* 0x44 - 0x5F: Reserved */28 __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */29 __R uint8_t RESERVED3[20]; /* 0x68 - 0x7B: Reserved */30 __R uint32_t CONFIG; /* 0x7C: Configuration Register */
14 __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */22 __R uint8_t RESERVED1[32]; /* 0x40 - 0x5F: Reserved */26 __R uint8_t RESERVED2[4]; /* 0x90 - 0x93: Reserved */28 __R uint8_t RESERVED3[8]; /* 0x98 - 0x9F: Reserved */31 __R uint8_t RESERVED4[8]; /* 0xA8 - 0xAF: Reserved */33 __R uint8_t RESERVED5[4]; /* 0xB4 - 0xB7: Reserved */37 __R uint8_t RESERVED6[24]; /* 0xC8 - 0xDF: Reserved */44 __R uint8_t RESERVED7[8]; /* 0xF8 - 0xFF: Reserved */45 __R uint32_t PRX[32]; /* 0x100 - 0x17C: APB RX FIFO Data Register. */
16 __R uint32_t RXREG; /* 0xC: Receive word message from other core. */18 __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */19 …__R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */
14 __R uint8_t RESERVED0[776]; /* 0x4F8 - 0x7FF: Reserved */21 __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */28 __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */35 __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */39 __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */42 __R uint8_t RESERVED4[1008]; /* 0x1010 - 0x13FF: Reserved */46 __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */49 __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */52 __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */56 __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */[all …]
14 __R uint8_t RESERVED0[648]; /* 0x578 - 0x7FF: Reserved */21 __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */28 __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */41 __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */45 __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */48 __R uint8_t RESERVED4[960]; /* 0x1040 - 0x13FF: Reserved */52 __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */55 __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */57 __R uint8_t RESERVED6[756]; /* 0x190C - 0x1BFF: Reserved */60 __R uint8_t RESERVED7[992]; /* 0x1C20 - 0x1FFF: Reserved */[all …]