| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/vin/vin-mipi/dphy/ |
| D | dphy_reg.c | 114 dphy_ctl[sel]->bits.module_en = 1; in dphy_enable()
119 dphy_ctl[sel]->bits.module_en = 0; in dphy_disable()
124 dphy_ctl[sel]->bits.lane_num = lane_num - 1; in dphy_set_data_lane()
129 return dphy_ctl[sel]->bits.lane_num + 1; in dphy_get_data_lane()
134 dphy_rx_ctl[sel]->bits.rx_clk_force = 1; in dphy_rx_enable()
137 dphy_rx_ctl[sel]->bits.rx_d3_force = 1; in dphy_rx_enable()
139 dphy_rx_ctl[sel]->bits.rx_d2_force = 1; in dphy_rx_enable()
141 dphy_rx_ctl[sel]->bits.rx_d1_force = 1; in dphy_rx_enable()
143 dphy_rx_ctl[sel]->bits.rx_d0_force = 1; in dphy_rx_enable()
146 dphy_rx_ctl[sel]->bits.rx_d3_force = 0; in dphy_rx_enable()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v2x/ |
| D | de_dsi.c | 53 return dsi_dev[sel]->dsi_basic_ctl1.bits.video_start_delay; in dsi_get_start_delay()
58 u32 curr_line = dsi_dev[sel]->dsi_debug_video0.bits.video_curr_line; in dsi_get_cur_line()
59 u32 vt = dsi_dev[sel]->dsi_basic_size1.bits.vt; in dsi_get_cur_line()
60 u32 vsa = dsi_dev[sel]->dsi_basic_size0.bits.vsa; in dsi_get_cur_line()
61 u32 vbp = dsi_dev[sel]->dsi_basic_size0.bits.vbp; in dsi_get_cur_line()
62 u32 y = dsi_dev[sel]->dsi_basic_size1.bits.vact; in dsi_get_cur_line()
74 dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en |= (1 << id); in dsi_irq_enable()
81 dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en &= ~(1 << id); in dsi_irq_disable()
90 en = dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en; in dsi_irq_query()
91 fl = dsi_dev[sel]->dsi_gint0.bits.dsi_irq_flag; in dsi_irq_query()
[all …]
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| D | de_lcd.c | 38 lcd_top[0]->vdpo_src_select.bits.vdpo0_src_sel = src; in vdpo_src_sel()
40 lcd_top[1]->vdpo_src_select.bits.vdpo1_src_sel = src; in vdpo_src_sel()
43 lcd_top[0]->vdpo_src_select.bits.vdpo0_src_sel = src; in vdpo_src_sel()
45 lcd_top[0]->vdpo_src_select.bits.vdpo1_src_sel = src; in vdpo_src_sel()
63 lcd_top[0]->dsi_src_select.bits.dsi0_src_sel = src; in dsi_src_sel()
65 lcd_top[1]->dsi_src_select.bits.dsi1_src_sel = src; in dsi_src_sel()
68 lcd_top[0]->dsi_src_select.bits.dsi0_src_sel = src; in dsi_src_sel()
70 lcd_top[0]->dsi_src_select.bits.dsi1_src_sel = src; in dsi_src_sel()
81 lcd_top[0]->tcon_tv_setup.bits.tv0_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
83 lcd_top[0]->tcon_tv_setup.bits.tv1_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
[all …]
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| D | de_lcd_sun50iw10.c | 39 lcd_top[0]->vdpo_src_select.bits.vdpo0_src_sel = src; in vdpo_src_sel()
41 lcd_top[1]->vdpo_src_select.bits.vdpo1_src_sel = src; in vdpo_src_sel()
44 lcd_top[0]->vdpo_src_select.bits.vdpo0_src_sel = src; in vdpo_src_sel()
46 lcd_top[0]->vdpo_src_select.bits.vdpo1_src_sel = src; in vdpo_src_sel()
64 lcd_top[0]->dsi_src_select.bits.dsi0_src_sel = src; in dsi_src_sel()
66 lcd_top[1]->dsi_src_select.bits.dsi1_src_sel = src; in dsi_src_sel()
69 lcd_top[0]->dsi_src_select.bits.dsi0_src_sel = src; in dsi_src_sel()
71 lcd_top[0]->dsi_src_select.bits.dsi1_src_sel = src; in dsi_src_sel()
82 lcd_top[0]->tcon_tv_setup.bits.tv0_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
84 lcd_top[0]->tcon_tv_setup.bits.tv1_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
[all …]
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| D | de_dsi_28.c | 111 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_0p_tx_lp = 0; in dsi_open()
112 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_1p_tx_lp = 0; in dsi_open()
113 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_2p_tx_lp = 0; in dsi_open()
114 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_0p_tx_lp = 0; in dsi_open()
115 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_1p_tx_lp = 0; in dsi_open()
116 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_2p_tx_lp = 0; in dsi_open()
117 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sw_0p_tx_lp = 0; in dsi_open()
118 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sw_1p_tx_lp = 0; in dsi_open()
119 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sr_0p_tx_lp = 0; in dsi_open()
120 dsi_dev[sel]->dsi_cmd_ctl.bits.max_rd_pkg_size_lp = 0; in dsi_open()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/ |
| D | de_dsi.c | 58 u32 dsi_start_delay = dsi_dev[sel]->dsi_basic_ctl1.bits.video_start_delay; in dsi_get_start_delay()
59 u32 vt = dsi_dev[sel]->dsi_basic_size1.bits.vt; in dsi_get_start_delay()
60 u32 vsa = dsi_dev[sel]->dsi_basic_size0.bits.vsa; in dsi_get_start_delay()
61 u32 vbp = dsi_dev[sel]->dsi_basic_size0.bits.vbp; in dsi_get_start_delay()
62 u32 y = dsi_dev[sel]->dsi_basic_size1.bits.vact; in dsi_get_start_delay()
66 if (start_delay > dsi_dev[sel]->dsi_basic_size1.bits.vt) in dsi_get_start_delay()
67 start_delay -= dsi_dev[sel]->dsi_basic_size1.bits.vt; in dsi_get_start_delay()
75 u32 curr_line = dsi_dev[sel]->dsi_debug_video0.bits.video_curr_line; in dsi_get_cur_line()
76 u32 vt = dsi_dev[sel]->dsi_basic_size1.bits.vt; in dsi_get_cur_line()
77 u32 vsa = dsi_dev[sel]->dsi_basic_size0.bits.vsa; in dsi_get_cur_line()
[all …]
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| D | de_lcd.c | 23 lcd_dev[0]->tcon_mul_ctl.bits.hdmi_src = sel; in hmdi_src_sel()
29 lcd_dev[0]->tcon_mul_ctl.bits.dsi_src = sel; in dsi_src_sel()
36 lcd_dev[sel]->tcon0_lvds_ctl.bits.tcon0_lvds_en = 1; in lvds_open()
38 lcd_dev[sel]->tcon0_lvds_ana[0].bits.c = 2; in lvds_open()
39 lcd_dev[sel]->tcon0_lvds_ana[0].bits.v = 3; in lvds_open()
40 lcd_dev[sel]->tcon0_lvds_ana[0].bits.pd = 2; in lvds_open()
41 lcd_dev[sel]->tcon0_lvds_ana[1].bits.c = 2; in lvds_open()
42 lcd_dev[sel]->tcon0_lvds_ana[1].bits.v = 3; in lvds_open()
43 lcd_dev[sel]->tcon0_lvds_ana[1].bits.pd = 2; in lvds_open()
45 lcd_dev[sel]->tcon0_lvds_ana[0].bits.en_ldo = 1; in lvds_open()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v33x/tcon/ |
| D | de_dsi.c | 53 return dsi_dev[sel]->dsi_basic_ctl1.bits.video_start_delay; in dsi_get_start_delay()
58 u32 curr_line = dsi_dev[sel]->dsi_debug_video0.bits.video_curr_line; in dsi_get_cur_line()
59 u32 vt = dsi_dev[sel]->dsi_basic_size1.bits.vt; in dsi_get_cur_line()
60 u32 vsa = dsi_dev[sel]->dsi_basic_size0.bits.vsa; in dsi_get_cur_line()
61 u32 vbp = dsi_dev[sel]->dsi_basic_size0.bits.vbp; in dsi_get_cur_line()
62 u32 y = dsi_dev[sel]->dsi_basic_size1.bits.vact; in dsi_get_cur_line()
74 dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en |= (1 << id); in dsi_irq_enable()
81 dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en &= ~(1 << id); in dsi_irq_disable()
90 en = dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en; in dsi_irq_query()
91 fl = dsi_dev[sel]->dsi_gint0.bits.dsi_irq_flag; in dsi_irq_query()
[all …]
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| D | de_lcd.c | 32 lcd_top[0]->tcon_tv_setup.bits.rgb0_src_sel = src; in rgb_src_sel()
48 lcd_top[0]->dsi_src_select.bits.dsi0_src_sel = src; in dsi_src_sel()
50 lcd_top[0]->dsi_src_select.bits.dsi1_src_sel = src; in dsi_src_sel()
61 lcd_top[0]->tcon_tv_setup.bits.tv0_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
63 lcd_top[0]->tcon_tv_setup.bits.tv1_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
75 lcd_top[0]->tcon_tv_setup.bits.tv0_out = TV_TO_GPIO; in tcon1_out_to_gpio()
77 lcd_top[0]->tcon_tv_setup.bits.tv1_out = TV_TO_GPIO; in tcon1_out_to_gpio()
91 lcd_top[0]->tcon_tv_setup.bits.tv0_clk_src = TV_CLK_F_TVE; in tcon1_tv_clk_enable()
92 lcd_top[0]->tcon_clk_gate.bits.tv0_clk_gate = en; in tcon1_tv_clk_enable()
94 lcd_top[0]->tcon_tv_setup.bits.tv1_clk_src = TV_CLK_F_TVE; in tcon1_tv_clk_enable()
[all …]
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| D | de_dsi_28.c | 113 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_0p_tx_lp = 0; in dsi_open()
114 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_1p_tx_lp = 0; in dsi_open()
115 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_2p_tx_lp = 0; in dsi_open()
116 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_0p_tx_lp = 0; in dsi_open()
117 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_1p_tx_lp = 0; in dsi_open()
118 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_2p_tx_lp = 0; in dsi_open()
119 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sw_0p_tx_lp = 0; in dsi_open()
120 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sw_1p_tx_lp = 0; in dsi_open()
121 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sr_0p_tx_lp = 0; in dsi_open()
122 dsi_dev[sel]->dsi_cmd_ctl.bits.max_rd_pkg_size_lp = 0; in dsi_open()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v3x/ |
| D | de_dsi.c | 53 return dsi_dev[sel]->dsi_basic_ctl1.bits.video_start_delay; in dsi_get_start_delay()
58 u32 curr_line = dsi_dev[sel]->dsi_debug_video0.bits.video_curr_line; in dsi_get_cur_line()
59 u32 vt = dsi_dev[sel]->dsi_basic_size1.bits.vt; in dsi_get_cur_line()
60 u32 vsa = dsi_dev[sel]->dsi_basic_size0.bits.vsa; in dsi_get_cur_line()
61 u32 vbp = dsi_dev[sel]->dsi_basic_size0.bits.vbp; in dsi_get_cur_line()
62 u32 y = dsi_dev[sel]->dsi_basic_size1.bits.vact; in dsi_get_cur_line()
74 dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en |= (1 << id); in dsi_irq_enable()
81 dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en &= ~(1 << id); in dsi_irq_disable()
90 en = dsi_dev[sel]->dsi_gint0.bits.dsi_irq_en; in dsi_irq_query()
91 fl = dsi_dev[sel]->dsi_gint0.bits.dsi_irq_flag; in dsi_irq_query()
[all …]
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| D | de_lcd.c | 32 lcd_top[0]->tcon_tv_setup.bits.rgb0_src_sel = src; in rgb_src_sel()
48 lcd_top[0]->dsi_src_select.bits.dsi0_src_sel = src; in dsi_src_sel()
50 lcd_top[0]->dsi_src_select.bits.dsi1_src_sel = src; in dsi_src_sel()
61 lcd_top[0]->tcon_tv_setup.bits.tv0_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
63 lcd_top[0]->tcon_tv_setup.bits.tv1_out = LCD_TO_GPIO; in tcon0_out_to_gpio()
75 lcd_top[0]->tcon_tv_setup.bits.tv0_out = TV_TO_GPIO; in tcon1_out_to_gpio()
77 lcd_top[0]->tcon_tv_setup.bits.tv1_out = TV_TO_GPIO; in tcon1_out_to_gpio()
91 lcd_top[0]->tcon_tv_setup.bits.tv0_clk_src = TV_CLK_F_TVE; in tcon1_tv_clk_enable()
92 lcd_top[0]->tcon_clk_gate.bits.tv0_clk_gate = en; in tcon1_tv_clk_enable()
94 lcd_top[0]->tcon_tv_setup.bits.tv1_clk_src = TV_CLK_F_TVE; in tcon1_tv_clk_enable()
[all …]
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| D | de_dsi_28.c | 113 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_0p_tx_lp = 0; in dsi_open()
114 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_1p_tx_lp = 0; in dsi_open()
115 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sw_2p_tx_lp = 0; in dsi_open()
116 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_0p_tx_lp = 0; in dsi_open()
117 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_1p_tx_lp = 0; in dsi_open()
118 dsi_dev[sel]->dsi_cmd_ctl.bits.gen_sr_2p_tx_lp = 0; in dsi_open()
119 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sw_0p_tx_lp = 0; in dsi_open()
120 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sw_1p_tx_lp = 0; in dsi_open()
121 dsi_dev[sel]->dsi_cmd_ctl.bits.dcs_sr_0p_tx_lp = 0; in dsi_open()
122 dsi_dev[sel]->dsi_cmd_ctl.bits.max_rd_pkg_size_lp = 0; in dsi_open()
[all …]
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| D | de_rtmx_type.h | 27 } bits; member
42 } bits; member
51 } bits; member
62 } bits; member
71 } bits; member
101 } bits; member
112 } bits; member
121 } bits; member
129 } bits; member
137 } bits; member
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/regs/ |
| D | hdmi_reg_tx.c | 44 tmp.bits.tmds_pack_mode = tmds_pack_mode; in hdmi_reg_tmds_pack_mode_set()
57 tmp.bits.avi_pkt_hb2 = hb2; in hdmi_reg_avi_pkt_header_hb_set()
58 tmp.bits.avi_pkt_hb1 = hb1; in hdmi_reg_avi_pkt_header_hb_set()
59 tmp.bits.avi_pkt_hb0 = hb0; in hdmi_reg_avi_pkt_header_hb_set()
73 tmp.bits.avi_sub_pkt0_pb3 = avi_pkt0_pb3; in hdmi_reg_avi_pkt0_low_set()
74 tmp.bits.avi_sub_pkt0_pb2 = avi_pkt0_pb2; in hdmi_reg_avi_pkt0_low_set()
75 tmp.bits.avi_sub_pkt0_pb1 = avi_pkt0_pb1; in hdmi_reg_avi_pkt0_low_set()
76 tmp.bits.avi_sub_pkt0_pb0 = avi_pkt0_pb0; in hdmi_reg_avi_pkt0_low_set()
89 tmp.bits.avi_sub_pkt0_pb6 = avi_pkt0_pb6; in hdmi_reg_avi_pkt0_high_set()
90 tmp.bits.avi_sub_pkt0_pb5 = avi_pkt0_pb5; in hdmi_reg_avi_pkt0_high_set()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/vin/vin-mipi/protocol/ |
| D | protocol_reg.c | 79 mipi_csi2_ctl[sel]->bits.rst = 1; in ptcl_enable()
80 mipi_csi2_ctl[sel]->bits.en = 1; in ptcl_enable()
85 mipi_csi2_ctl[sel]->bits.en = 0; in ptcl_disable()
86 mipi_csi2_ctl[sel]->bits.rst = 0; in ptcl_disable()
91 mipi_csi2_cfg[sel]->bits.dl_cfg = lane_num - 1; in ptcl_set_data_lane()
96 return mipi_csi2_cfg[sel]->bits.dl_cfg + 1; in ptcl_get_data_lane()
101 mipi_csi2_cfg[sel]->bits.pl_bit_ord = pl_bit_ord; in ptcl_set_pl_bit_order()
106 return (enum bit_order)mipi_csi2_cfg[sel]->bits.pl_bit_ord; in ptcl_get_pl_bit_order()
111 mipi_csi2_cfg[sel]->bits.ph_bit_ord = ph_bit_ord; in ptcl_set_ph_bit_order()
116 return (enum bit_order)mipi_csi2_cfg[sel]->bits.ph_bit_ord; in ptcl_get_ph_bit_order()
[all …]
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/tde/driver/src/adp/tde_v2_0/ |
| D | tde_hal_k.c | 44 (node)->src1_cbmpara.bits.s1_blendmode = (a); \
45 (node)->src2_cbmpara.bits.s2_blendmode = (b); \
181 (hw_node->src2_fill.bits.src2_color_fill) |= (cell << (i * bpp)); in tde_fill_data_by_fmt()
183 (hw_node->src1_fill.bits.src1_color_fill) |= (cell << (i * bpp)); in tde_fill_data_by_fmt()
188 (hw_node->src2_fill.bits.src2_color_fill) = data; in tde_fill_data_by_fmt()
190 (hw_node->src1_fill.bits.src1_color_fill) = data; in tde_fill_data_by_fmt()
527 hw_node->tde_intmask.bits.eof_mask = 0; in tde_hal_node_enable_complete_int()
528 hw_node->tde_intmask.bits.timeout_mask = 0x1; in tde_hal_node_enable_complete_int()
529 hw_node->tde_intmask.bits.bus_err_mask = 0x1; in tde_hal_node_enable_complete_int()
531 hw_node->tde_intmask.bits.eof_end_mask = 0x0; in tde_hal_node_enable_complete_int()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_sun8iw8/ |
| D | de_lcd.c | 20 lcd_dev[0]->tcon_mul_ctl.bits.hdmi_src = sel; in hmdi_src_sel()
26 lcd_dev[0]->tcon_mul_ctl.bits.dsi_src = sel; in dsi_src_sel()
33 lcd_dev[sel]->tcon0_lvds_ctl.bits.tcon0_lvds_en = 1; in lvds_open()
35 lcd_dev[sel]->tcon0_lvds_ana[0].bits.c = 2; in lvds_open()
36 lcd_dev[sel]->tcon0_lvds_ana[0].bits.v = 3; in lvds_open()
37 lcd_dev[sel]->tcon0_lvds_ana[0].bits.pd = 2; in lvds_open()
38 lcd_dev[sel]->tcon0_lvds_ana[1].bits.c = 2; in lvds_open()
39 lcd_dev[sel]->tcon0_lvds_ana[1].bits.v = 3; in lvds_open()
40 lcd_dev[sel]->tcon0_lvds_ana[1].bits.pd = 2; in lvds_open()
42 lcd_dev[sel]->tcon0_lvds_ana[0].bits.en_ldo = 1; in lvds_open()
[all …]
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/vo/vo_dev/arch/hi3516cv500/include/ |
| D | vou_reg.h | 40 } bits; member
71 } bits; member
102 } bits; member
133 } bits; member
157 } bits; member
188 } bits; member
219 } bits; member
250 } bits; member
276 } bits; member
297 } bits; member
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hifb/drv/hi3516cv500/ |
| D | hifb_reg.h | 39 } bits; member
70 } bits; member
101 } bits; member
132 } bits; member
163 } bits; member
194 } bits; member
225 } bits; member
239 } bits; member
253 } bits; member
264 } bits; member
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| /device/soc/hisilicon/common/platform/mipi_csi/ |
| D | mipi_rx_reg.h | 40 } bits; member
62 } bits; member
84 } bits; member
103 } bits; member
117 } bits; member
131 } bits; member
145 } bits; member
165 } bits; member
177 } bits; member
189 } bits; member
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| /device/soc/hisilicon/hi3751v350/sdk_linux/source/common/drv/include/sysreg/hi3751v350/ |
| D | hi_reg_peri.h | 99 } bits; member
124 } bits; member
203 } bits; member
253 } bits; member
278 } bits; member
309 } bits; member
334 } bits; member
358 } bits; member
382 } bits; member
404 } bits; member
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| D | hi_reg_crg.h | 51 } bits; member
137 } bits; member
172 } bits; member
258 } bits; member
293 } bits; member
379 } bits; member
414 } bits; member
500 } bits; member
535 } bits; member
621 } bits; member
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/hi3516cv500/mipi_rx/ |
| D | mipi_rx_reg.h | 43 } bits; member
65 } bits; member
87 } bits; member
106 } bits; member
120 } bits; member
134 } bits; member
148 } bits; member
168 } bits; member
180 } bits; member
192 } bits; member
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/g2d/g2d_rcq/ |
| D | g2d_top.c | 33 mixer_glb->mixer_ctrl.bits.scan_order = scan_order; in g2d_mixer_scan_order_fun()
38 mixer_glb->mixer_ctrl.bits.start = start; in g2d_mixer_start()
43 mixer_glb->mixer_interrupt.bits.finish_irq_en = en; in g2d_mixer_irq_en()
48 if (mixer_glb->mixer_interrupt.bits.mixer_irq & 0x1) { in g2d_mixer_irq_query()
49 mixer_glb->mixer_interrupt.bits.mixer_irq = 1; in g2d_mixer_irq_query()
57 g2d_top->sclk_gate.bits.mixer_sclk_gate = 1; in g2d_bsp_open()
58 g2d_top->sclk_gate.bits.rot_sclk_gate = 1; in g2d_bsp_open()
59 g2d_top->hclk_gate.bits.mixer_hclk_gate = 1; in g2d_bsp_open()
60 g2d_top->hclk_gate.bits.rot_hclk_gate = 1; in g2d_bsp_open()
61 g2d_top->ahb_rst.bits.mixer_ahb_rst = 1; in g2d_bsp_open()
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