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Searched refs:cntlr (Results 1 – 25 of 41) sorted by relevance

12

/device/soc/hisilicon/common/platform/mtd/hifmc100/common/
Dhifmc100.c85 const struct DeviceResourceNode *HifmcCntlrGetDevTableNode(struct HifmcCntlr *cntlr) in HifmcCntlrGetDevTableNode() argument
96 if (cntlr->flashType == HIFMC_CFG_TYPE_SPI_NOR) { in HifmcCntlrGetDevTableNode()
97 tableNode = drsOps->GetChildNode(cntlr->drsNode, "spi_nor_dev_table"); in HifmcCntlrGetDevTableNode()
99 tableNode = drsOps->GetChildNode(cntlr->drsNode, "spi_nand_dev_table"); in HifmcCntlrGetDevTableNode()
108 static int32_t HifmcCntlrSearchDevInfo(struct HifmcCntlr *cntlr, struct SpiFlash *spi) in HifmcCntlrSearchDevInfo() argument
110 if (cntlr->flashType == HIFMC_CFG_TYPE_SPI_NOR) { in HifmcCntlrSearchDevInfo()
111 return HifmcCntlrSearchSpinorInfo(cntlr, spi); in HifmcCntlrSearchDevInfo()
113 return HifmcCntlrSearchSpinandInfo(cntlr, spi); in HifmcCntlrSearchDevInfo()
117 static int32_t HifmcCntlrReadDrs(struct HifmcCntlr *cntlr) in HifmcCntlrReadDrs() argument
129 node = cntlr->drsNode; in HifmcCntlrReadDrs()
[all …]
/device/soc/hisilicon/common/platform/dmac/
Ddmac_hi35xx.c78 static int HiDmacIsrErrProc(struct DmaCntlr *cntlr, uint16_t chan) in HiDmacIsrErrProc() argument
82 chanErrStats[ERROR_STATUS_NUM_0] = OSAL_READL(cntlr->remapBase + HIDMAC_INT_ERR1_OFFSET); in HiDmacIsrErrProc()
84 chanErrStats[ERROR_STATUS_NUM_1] = OSAL_READL(cntlr->remapBase + HIDMAC_INT_ERR2_OFFSET); in HiDmacIsrErrProc()
86 chanErrStats[ERROR_STATUS_NUM_2] = OSAL_READL(cntlr->remapBase + HIDMAC_INT_ERR3_OFFSET); in HiDmacIsrErrProc()
93 OSAL_WRITEL(1 << chan, cntlr->remapBase + HIDMAC_INT_ERR1_RAW_OFFSET); in HiDmacIsrErrProc()
94 … HDF_LOGE("HIDMAC_INT_ERR1_RAW = 0x%x", OSAL_READL(cntlr->remapBase + HIDMAC_INT_ERR1_RAW_OFFSET)); in HiDmacIsrErrProc()
95 OSAL_WRITEL(1 << chan, cntlr->remapBase + HIDMAC_INT_ERR2_RAW_OFFSET); in HiDmacIsrErrProc()
96 … HDF_LOGE("HIDMAC_INT_ERR2_RAW = 0x%x", OSAL_READL(cntlr->remapBase + HIDMAC_INT_ERR2_RAW_OFFSET)); in HiDmacIsrErrProc()
97 OSAL_WRITEL(1 << chan, cntlr->remapBase + HIDMAC_INT_ERR3_RAW_OFFSET); in HiDmacIsrErrProc()
98 … HDF_LOGE("HIDMAC_INT_ERR3_RAW = 0x%x", OSAL_READL(cntlr->remapBase + HIDMAC_INT_ERR3_RAW_OFFSET)); in HiDmacIsrErrProc()
[all …]
/device/soc/hisilicon/common/platform/mtd/hifmc100/spi_nand/
Dhifmc100_spi_nand.c114 int32_t HifmcCntlrSearchSpinandInfo(struct HifmcCntlr *cntlr, struct SpiFlash *spi) in HifmcCntlrSearchSpinandInfo() argument
122 tableNode = HifmcCntlrGetDevTableNode(cntlr); in HifmcCntlrSearchSpinandInfo()
145 uint8_t HifmcCntlrReadSpinandReg(struct HifmcCntlr *cntlr, struct SpiFlash *spi, uint8_t cmd) in HifmcCntlrReadSpinandReg() argument
154 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_CFG_REG_OFF); in HifmcCntlrReadSpinandReg()
162 HIFMC_REG_WRITE(cntlr, reg, HIFMC_CMD_REG_OFF); in HifmcCntlrReadSpinandReg()
165 HIFMC_REG_WRITE(cntlr, reg, HIFMC_DATA_NUM_REG_OFF); in HifmcCntlrReadSpinandReg()
172 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_REG_OFF); in HifmcCntlrReadSpinandReg()
174 HIFMC_CMD_WAIT_CPU_FINISH(cntlr); in HifmcCntlrReadSpinandReg()
177 status = HIFMC_REG_READ(cntlr, HIFMC_FLASH_INFO_REG_OFF); in HifmcCntlrReadSpinandReg()
179 status = OSAL_READB(cntlr->memBase); in HifmcCntlrReadSpinandReg()
[all …]
Dhifmc100_spi_nand_ids.c24 struct HifmcCntlr *cntlr = NULL; in HifmcCntlrSpinandWaitReadyDefault() local
29 if (spi == NULL || spi->mtd.cntlr == NULL) { in HifmcCntlrSpinandWaitReadyDefault()
32 cntlr = spi->mtd.cntlr; in HifmcCntlrSpinandWaitReadyDefault()
35 ret = HifmcCntlrDevFeatureOp(cntlr, spi, true, MTD_SPI_NAND_STATUS_ADDR, &status); in HifmcCntlrSpinandWaitReadyDefault()
50 struct HifmcCntlr *cntlr = NULL; in HifmcCntlrSpinandWriteEnableDefault() local
55 if (spi == NULL || spi->mtd.cntlr == NULL) { in HifmcCntlrSpinandWriteEnableDefault()
58 cntlr = spi->mtd.cntlr; in HifmcCntlrSpinandWriteEnableDefault()
60 ret = HifmcCntlrDevFeatureOp(cntlr, spi, true, MTD_SPI_NAND_STATUS_ADDR, &status); in HifmcCntlrSpinandWriteEnableDefault()
72 reg = HIFMC_REG_READ(cntlr, HIFMC_GLOBAL_CFG_REG_OFF); in HifmcCntlrSpinandWriteEnableDefault()
75 HIFMC_REG_WRITE(cntlr, reg, HIFMC_GLOBAL_CFG_REG_OFF); in HifmcCntlrSpinandWriteEnableDefault()
[all …]
Dhifmc100_spi_nand.h22 int32_t HifmcCntlrSearchSpinandInfo(struct HifmcCntlr *cntlr, struct SpiFlash *spi);
23 int32_t HifmcCntlrInitSpinandDevice(struct HifmcCntlr *cntlr, struct SpiFlash *spi);
24 int32_t HifmcCntlrReadIdSpiNand(struct HifmcCntlr *cntlr, uint8_t cs, uint8_t *id, size_t len);
25 int32_t HifmcCntlrInitOob(struct HifmcCntlr *cntlr, struct SpiFlash *spi);
26 uint8_t HifmcCntlrReadSpinandReg(struct HifmcCntlr *cntlr, struct SpiFlash *spi, uint8_t cmd);
28 int32_t HifmcCntlrDevFeatureOp(struct HifmcCntlr *cntlr, struct SpiFlash *spi,
/device/qemu/drivers/virtio/
Dfakesdio.c85 static void FakeSdioDeleteCntlr(struct MmcCntlr *cntlr) in FakeSdioDeleteCntlr() argument
87 if (cntlr == NULL) { in FakeSdioDeleteCntlr()
90 if (cntlr->curDev != NULL) { in FakeSdioDeleteCntlr()
91 MmcDeviceRemove(cntlr->curDev); in FakeSdioDeleteCntlr()
92 OsalMemFree(cntlr->curDev); in FakeSdioDeleteCntlr()
94 MmcCntlrRemove(cntlr); in FakeSdioDeleteCntlr()
95 OsalMemFree(cntlr); in FakeSdioDeleteCntlr()
98 static int32_t FakeSdioCntlrParse(struct MmcCntlr *cntlr, struct HdfDeviceObject *obj) in FakeSdioCntlrParse() argument
104 if (obj == NULL || cntlr == NULL) { in FakeSdioCntlrParse()
120 ret = drsOps->GetUint16(node, "hostId", &(cntlr->index), 0); in FakeSdioCntlrParse()
[all …]
Dvirtblock.c411 static int32_t VirtMmcIO(const struct MmcCntlr *cntlr, const struct MmcCmd *cmd) in VirtMmcIO() argument
413 struct Virtblk *blk = cntlr->priv; in VirtMmcIO()
417 if (cntlr->curDev->state.bits.blockAddr == 0) { in VirtMmcIO()
438 static int32_t VirtMmcDoRequest(struct MmcCntlr *cntlr, struct MmcCmd *cmd) in VirtMmcDoRequest() argument
440 if ((cntlr == NULL) || (cntlr->priv == NULL) || (cmd == NULL)) { in VirtMmcDoRequest()
443 struct Virtblk *blk = cntlr->priv; in VirtMmcDoRequest()
476 return VirtMmcIO(cntlr, cmd); in VirtMmcDoRequest()
484 static bool VirtMmcPlugged(struct MmcCntlr *cntlr) in VirtMmcPlugged() argument
486 (void)cntlr; in VirtMmcPlugged()
490 static bool VirtMmcBusy(struct MmcCntlr *cntlr) in VirtMmcBusy() argument
[all …]
/device/soc/hisilicon/common/platform/mtd/hifmc100/spi_nor/
Dw25qh.c29 struct HifmcCntlr *cntlr = NULL; in HifmcCntlrSpinorEntry4AddrW25qh() local
31 if (spi == NULL || spi->mtd.cntlr == NULL) { in HifmcCntlrSpinorEntry4AddrW25qh()
34 cntlr = spi->mtd.cntlr; in HifmcCntlrSpinorEntry4AddrW25qh()
44 status = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR3); in HifmcCntlrSpinorEntry4AddrW25qh()
53 HIFMC_REG_WRITE(cntlr, reg, HIFMC_CMD_REG_OFF); in HifmcCntlrSpinorEntry4AddrW25qh()
56 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_CFG_REG_OFF); in HifmcCntlrSpinorEntry4AddrW25qh()
59 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_REG_OFF); in HifmcCntlrSpinorEntry4AddrW25qh()
61 HIFMC_CMD_WAIT_CPU_FINISH(cntlr); in HifmcCntlrSpinorEntry4AddrW25qh()
64 status = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR3); in HifmcCntlrSpinorEntry4AddrW25qh()
75 HIFMC_REG_WRITE(cntlr, reg, HIFMC_CMD_REG_OFF); in HifmcCntlrSpinorEntry4AddrW25qh()
[all …]
Dhifmc100_spi_nor_ids.c24 struct HifmcCntlr *cntlr = NULL; in HifmcCntlrSpinorWaitReadyDefault() local
28 if (spi == NULL || spi->mtd.cntlr == NULL) { in HifmcCntlrSpinorWaitReadyDefault()
31 cntlr = spi->mtd.cntlr; in HifmcCntlrSpinorWaitReadyDefault()
34 status = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR); in HifmcCntlrSpinorWaitReadyDefault()
46 struct HifmcCntlr *cntlr = NULL; in HifmcCntlrSpinorWriteEnableDefault() local
49 if (spi == NULL || spi->mtd.cntlr == NULL) { in HifmcCntlrSpinorWriteEnableDefault()
52 cntlr = spi->mtd.cntlr; in HifmcCntlrSpinorWriteEnableDefault()
54 reg = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR); in HifmcCntlrSpinorWriteEnableDefault()
64 reg = HIFMC_REG_READ(cntlr, HIFMC_GLOBAL_CFG_REG_OFF); in HifmcCntlrSpinorWriteEnableDefault()
67 HIFMC_REG_WRITE(cntlr, reg, HIFMC_GLOBAL_CFG_REG_OFF); in HifmcCntlrSpinorWriteEnableDefault()
[all …]
Dhifmc100_spi_nor.c90 int32_t HifmcCntlrSearchSpinorInfo(struct HifmcCntlr *cntlr, struct SpiFlash *spi) in HifmcCntlrSearchSpinorInfo() argument
98 tableNode = HifmcCntlrGetDevTableNode(cntlr); in HifmcCntlrSearchSpinorInfo()
128 uint8_t HifmcCntlrReadSpinorReg(struct HifmcCntlr *cntlr, struct SpiFlash *spi, uint8_t cmd) in HifmcCntlrReadSpinorReg() argument
137 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_CFG_REG_OFF); in HifmcCntlrReadSpinorReg()
145 HIFMC_REG_WRITE(cntlr, reg, HIFMC_CMD_REG_OFF); in HifmcCntlrReadSpinorReg()
148 HIFMC_REG_WRITE(cntlr, reg, HIFMC_DATA_NUM_REG_OFF); in HifmcCntlrReadSpinorReg()
155 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_REG_OFF); in HifmcCntlrReadSpinorReg()
157 HIFMC_CMD_WAIT_CPU_FINISH(cntlr); in HifmcCntlrReadSpinorReg()
160 status = HIFMC_REG_READ(cntlr, HIFMC_FLASH_INFO_REG_OFF); in HifmcCntlrReadSpinorReg()
162 status = OSAL_READB(cntlr->memBase); in HifmcCntlrReadSpinorReg()
[all …]
Dmx25l.c28 struct HifmcCntlr *cntlr = NULL; in HifmcCntlrSpinorQeEnableMx25l() local
30 if (spi == NULL || spi->mtd.cntlr == NULL) { in HifmcCntlrSpinorQeEnableMx25l()
33 cntlr = spi->mtd.cntlr; in HifmcCntlrSpinorQeEnableMx25l()
38 status = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR); in HifmcCntlrSpinorQeEnableMx25l()
51 OSAL_WRITEB(status, cntlr->memBase); in HifmcCntlrSpinorQeEnableMx25l()
54 HIFMC_REG_WRITE(cntlr, reg, HIFMC_CMD_REG_OFF); in HifmcCntlrSpinorQeEnableMx25l()
57 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_CFG_REG_OFF); in HifmcCntlrSpinorQeEnableMx25l()
60 HIFMC_REG_WRITE(cntlr, reg, HIFMC_DATA_NUM_REG_OFF); in HifmcCntlrSpinorQeEnableMx25l()
65 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_REG_OFF); in HifmcCntlrSpinorQeEnableMx25l()
69 status = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR); in HifmcCntlrSpinorQeEnableMx25l()
/device/soc/hisilicon/common/platform/mipi_csi/
Dmipi_csi_hi35xx.c48 static bool MipiIsHsModeCfged(struct MipiCsiCntlr *cntlr) in MipiIsHsModeCfged() argument
52 OsalSpinLock(&cntlr->ctxLock); in MipiIsHsModeCfged()
53 hsModeCfged = cntlr->ctx.hsModeCfged; in MipiIsHsModeCfged()
54 OsalSpinUnlock(&cntlr->ctxLock); in MipiIsHsModeCfged()
59 static bool MipiIsDevValid(struct MipiCsiCntlr *cntlr, uint8_t devno) in MipiIsDevValid() argument
63 OsalSpinLock(&cntlr->ctxLock); in MipiIsDevValid()
64 devValid = cntlr->ctx.devValid[devno]; in MipiIsDevValid()
65 OsalSpinUnlock(&cntlr->ctxLock); in MipiIsDevValid()
70 static bool MipiIsDevCfged(struct MipiCsiCntlr *cntlr, uint8_t devno) in MipiIsDevCfged() argument
74 OsalSpinLock(&cntlr->ctxLock); in MipiIsDevCfged()
[all …]
/device/soc/telink/b91/hdf/
Dgpio_telink.c31 struct GpioCntlr cntlr; member
120 static int32_t GpioDevWrite(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t val);
121 static int32_t GpioDevRead(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t *val);
122 static int32_t GpioDevSetDir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t dir);
123 static int32_t GpioDevGetDir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t *dir);
124 static int32_t GpioDevSetIrq(struct GpioCntlr *cntlr, uint16_t local, uint16_t mode);
125 static int32_t GpioDevEnableIrq(struct GpioCntlr *cntlr, uint16_t local);
126 static int32_t GpioDevDisableIrq(struct GpioCntlr *cntlr, uint16_t local);
127 static int32_t GpioDevUnsetIrq(struct GpioCntlr *cntlr, uint16_t local);
150 GpioCntlrIrqCallback(&pB91GpioCntlr->cntlr, i); in GpioIrqHandler()
[all …]
/device/soc/hisilicon/common/platform/i2s/
Di2s_hi35xx.c145 static int32_t Hi35xxI2sEnable(struct I2sCntlr *cntlr) in Hi35xxI2sEnable() argument
147 if (cntlr == NULL || cntlr->priv == NULL) { in Hi35xxI2sEnable()
154 static int32_t Hi35xxI2sDisable(struct I2sCntlr *cntlr) in Hi35xxI2sDisable() argument
156 if (cntlr == NULL || cntlr->priv == NULL) { in Hi35xxI2sDisable()
161 struct I2sConfigInfo *i2sCfg = (struct I2sConfigInfo *)cntlr->priv; in Hi35xxI2sDisable()
171 static int32_t Hi35xxI2sOpen(struct I2sCntlr *cntlr) in Hi35xxI2sOpen() argument
173 (void)cntlr; in Hi35xxI2sOpen()
177 static int32_t Hi35xxI2sClose(struct I2sCntlr *cntlr) in Hi35xxI2sClose() argument
179 (void)cntlr; in Hi35xxI2sClose()
183 static int32_t Hi35xxI2sGetCfg(struct I2sCntlr *cntlr, struct I2sCfg *cfg) in Hi35xxI2sGetCfg() argument
[all …]
/device/soc/st/common/platform/gpio/
Dstm32mp1_gpio.c19 static inline struct Mp1xxGpioCntlr *ToMp1xxGpioCntlr(struct GpioCntlr *cntlr) in ToMp1xxGpioCntlr() argument
21 return (struct Mp1xxGpioCntlr *)cntlr; in ToMp1xxGpioCntlr()
38 static int32_t Mp1xxGetGroupByGpioNum(struct GpioCntlr *cntlr, uint16_t gpio, struct GpioGroup **gr… in Mp1xxGetGroupByGpioNum() argument
43 if (cntlr == NULL || cntlr->priv == NULL) { in Mp1xxGetGroupByGpioNum()
47 stm32gpio = ToMp1xxGpioCntlr(cntlr); in Mp1xxGetGroupByGpioNum()
57 static int32_t Mp1xxGpioSetDir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t dir) in Mp1xxGpioSetDir() argument
67 ret = Mp1xxGetGroupByGpioNum(cntlr, gpio, &group); in Mp1xxGpioSetDir()
89 static int32_t Mp1xxGpioGetDir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t *dir) in Mp1xxGpioGetDir() argument
97 ret = Mp1xxGetGroupByGpioNum(cntlr, gpio, &group); in Mp1xxGpioGetDir()
111 static int32_t Mp1xxGpioWrite(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t val) in Mp1xxGpioWrite() argument
[all …]
/device/soc/bestechnic/bes2600/liteos_m/components/drivers/mipi_dsi/
Dmipi_dsi.c126 static int32_t MipiDsiDevSetCntlrCfg(struct MipiDsiCntlr *cntlr) in MipiDsiDevSetCntlrCfg() argument
129 uint8_t dsi_lane = (uint8_t)cntlr->cfg.lane; in MipiDsiDevSetCntlrCfg()
130 uint32_t dsi_bitclk = cntlr->cfg.phyDataRate; in MipiDsiDevSetCntlrCfg()
131 uint32_t dsi_pclk = cntlr->cfg.pixelClk; in MipiDsiDevSetCntlrCfg()
132 priv.cfg.active_width = cntlr->cfg.timing.xPixels; in MipiDsiDevSetCntlrCfg()
133 priv.cfg.active_height = cntlr->cfg.timing.ylines; in MipiDsiDevSetCntlrCfg()
135 if (cntlr->cfg.mode == DSI_CMD_MODE) { in MipiDsiDevSetCntlrCfg()
138 } else if (cntlr->cfg.mode == DSI_VIDEO_MODE) { in MipiDsiDevSetCntlrCfg()
141 priv.mode = cntlr->cfg.mode; in MipiDsiDevSetCntlrCfg()
142 priv.cfg.h_back_porch = cntlr->cfg.timing.hbpPixels; in MipiDsiDevSetCntlrCfg()
[all …]
/device/soc/rockchip/rk2206/hdf_driver/gpio/
Dgpio_driver.c67 static int32_t iodrv_setdir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t dir) in iodrv_setdir() argument
69 if (cntlr == NULL) { in iodrv_setdir()
73 if (gpio >= cntlr->count) { in iodrv_setdir()
74 PRINT_ERR("%s: gpio(%d) >= cntlr->count(%d)", __func__, gpio, cntlr->count); in iodrv_setdir()
91 static int32_t iodrv_getdir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t *dir) in iodrv_getdir() argument
93 if (cntlr == NULL) { in iodrv_getdir()
97 if (gpio >= cntlr->count) { in iodrv_getdir()
98 PRINT_ERR("%s: gpio(%d) >= cntlr->count(%d)", __func__, gpio, cntlr->count); in iodrv_getdir()
123 static int32_t iodrv_write(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t value) in iodrv_write() argument
125 if (cntlr == NULL) { in iodrv_write()
[all …]
/device/soc/rockchip/rk2206/hdf_driver/i2c/
Di2c_driver.c265 static int32_t i2cdrv_transfer(struct I2cCntlr *cntlr, struct I2cMsg *msgs, int16_t count) in i2cdrv_transfer() argument
278 if (cntlr == NULL) { in i2cdrv_transfer()
282 if (cntlr->priv == NULL) { in i2cdrv_transfer()
291 bus = (struct i2c_bus *)cntlr->priv; in i2cdrv_transfer()
350 struct I2cCntlr *cntlr = NULL; in i2cdrv_init() local
359 cntlr = (struct I2cCntlr *)OsalMemAlloc(sizeof(struct I2cCntlr)); in i2cdrv_init()
362 if (cntlr == NULL) { in i2cdrv_init()
368 if (cntlr != NULL) { in i2cdrv_init()
369 OsalMemFree(cntlr); in i2cdrv_init()
370 cntlr = NULL; in i2cdrv_init()
[all …]
/device/soc/rockchip/rk2206/hardware/include/lz_hardware/
Dbase.h29 CNTLR_S *cntlr; \
37 cntlr = &g_cntlrs[id]; \
38 if (cntlr->init) { \
45 CNTLR_S *cntlr; \
53 cntlr = &g_cntlrs[id]; \
54 if (!cntlr->init) { \
61 CNTLR_S *cntlr; \
72 cntlr = &g_cntlrs[bank]; \
73 if (!cntlr->init) { \
74 if (finit(cntlr) != LZ_HARDWARE_SUCCESS) \
[all …]
/device/soc/hpmicro/drivers/platform/
Dspi.c39 static void HpmSpiConfig(struct SpiCntlr *cntlr) in HpmSpiConfig() argument
41 struct HPMSpiDevice *hpmSpiDev = (struct HPMSpiDevice *)cntlr->priv; in HpmSpiConfig()
79 static int32_t HpmSpiGetCfg(struct SpiCntlr *cntlr, struct SpiCfg *cfg) in HpmSpiGetCfg() argument
81 struct HPMSpiDevice *hpmSpiDev = (struct HPMSpiDevice *)cntlr->priv; in HpmSpiGetCfg()
87 static int32_t HpmSpiSetCfg(struct SpiCntlr *cntlr, struct SpiCfg *cfg) in HpmSpiSetCfg() argument
89 struct HPMSpiDevice *hpmSpiDev = (struct HPMSpiDevice *)cntlr->priv; in HpmSpiSetCfg()
92 HpmSpiConfig(cntlr); in HpmSpiSetCfg()
96 static int32_t HpmSpiTransfer(struct SpiCntlr *cntlr, struct SpiMsg *msg, uint32_t count) in HpmSpiTransfer() argument
99 struct HPMSpiDevice *hpmSpiDev = (struct HPMSpiDevice *)cntlr->priv; in HpmSpiTransfer()
135 static int32_t HpmSpiOpen(struct SpiCntlr *cntlr) in HpmSpiOpen() argument
[all …]
Di2c.c36 static int32_t hpmTransfer(struct I2cCntlr *cntlr, struct I2cMsg *msgs, int16_t count) in hpmTransfer() argument
38 struct HPMI2cDevice *hpmI2cDev = (struct HPMI2cDevice *)cntlr->priv; in hpmTransfer()
84 struct I2cCntlr *cntlr = (struct I2cCntlr *)OsalMemCalloc( in I2cDriverInit() local
86 if (cntlr == NULL) { in I2cDriverInit()
92 … struct HPMI2cDevice *hpmI2cDev = (struct HPMI2cDevice *)((char *)cntlr + sizeof(struct I2cCntlr)); in I2cDriverInit()
93 cntlr->priv = hpmI2cDev; in I2cDriverInit()
94 device->priv = cntlr; in I2cDriverInit()
110 cntlr->busId = hpmI2cDev->id; in I2cDriverInit()
111 cntlr->ops = &hpmI2cMethod; in I2cDriverInit()
112 ret = I2cCntlrAdd(cntlr); in I2cDriverInit()
[all …]
/device/soc/hisilicon/common/platform/mmc/himci_v200/
Dhimci.c53 static void HimciSetEmmcDrvCap(struct MmcCntlr *cntlr) in HimciSetEmmcDrvCap() argument
63 if (cntlr->curDev->workPara.timing == BUS_TIMING_MMC_HS200) { in HimciSetEmmcDrvCap()
65 } else if (cntlr->curDev->workPara.timing == BUS_TIMING_MMC_HS) { in HimciSetEmmcDrvCap()
68 if (cntlr->curDev->workPara.clock == 400000) { in HimciSetEmmcDrvCap()
88 static void HimciSetSdDrvCap(struct MmcCntlr *cntlr) in HimciSetSdDrvCap() argument
100 if (cntlr->curDev->workPara.timing == BUS_TIMING_UHS_SDR104) { in HimciSetSdDrvCap()
102 } else if (cntlr->curDev->workPara.timing == BUS_TIMING_UHS_SDR50) { in HimciSetSdDrvCap()
104 } else if (cntlr->curDev->workPara.timing == BUS_TIMING_UHS_SDR25) { in HimciSetSdDrvCap()
106 } else if (cntlr->curDev->workPara.timing == BUS_TIMING_UHS_SDR12) { in HimciSetSdDrvCap()
108 } else if (cntlr->curDev->workPara.timing == BUS_TIMING_SD_HS) { in HimciSetSdDrvCap()
[all …]
/device/soc/rockchip/rk2206/hdf_driver/spi/
Dspi_driver.c373 static int32_t spidrv_open(struct SpiCntlr *cntlr) in spidrv_open() argument
378 if (cntlr == NULL) { in spidrv_open()
382 if (cntlr->priv == NULL) { in spidrv_open()
387 params = (struct spi_params *)cntlr->priv; in spidrv_open()
398 static int32_t spidrv_close(struct SpiCntlr *cntlr) in spidrv_close() argument
402 if (cntlr == NULL) { in spidrv_close()
406 if (cntlr->priv == NULL) { in spidrv_close()
411 params = (struct spi_params *)cntlr->priv; in spidrv_close()
419 static int32_t spidrv_setcfg(struct SpiCntlr *cntlr, struct SpiCfg *cfg) in spidrv_setcfg() argument
423 if (cntlr == NULL) { in spidrv_setcfg()
[all …]
/device/soc/hisilicon/common/platform/pin/
Dpin_hi35xx.c39 struct PinCntlr cntlr; member
104 static int32_t Hi35xxPinSetPull(struct PinCntlr *cntlr, uint32_t index, enum PinPullType pullType) in Hi35xxPinSetPull() argument
109 hi35xx = (struct Hi35xxPinCntlr *)cntlr; in Hi35xxPinSetPull()
117 static int32_t Hi35xxPinGetPull(struct PinCntlr *cntlr, uint32_t index, enum PinPullType *pullType) in Hi35xxPinGetPull() argument
121 hi35xx = (struct Hi35xxPinCntlr *)cntlr; in Hi35xxPinGetPull()
129 static int32_t Hi35xxPinSetStrength(struct PinCntlr *cntlr, uint32_t index, uint32_t strength) in Hi35xxPinSetStrength() argument
134 hi35xx = (struct Hi35xxPinCntlr *)cntlr; in Hi35xxPinSetStrength()
142 static int32_t Hi35xxPinGetStrength(struct PinCntlr *cntlr, uint32_t index, uint32_t *strength) in Hi35xxPinGetStrength() argument
146 hi35xx = (struct Hi35xxPinCntlr *)cntlr; in Hi35xxPinGetStrength()
154 static int32_t Hi35xxPinSetFunc(struct PinCntlr *cntlr, uint32_t index, const char *funcName) in Hi35xxPinSetFunc() argument
[all …]
/device/soc/st/common/platform/i2c/
Dstm32mp1_i2c.c138 static int32_t Mp1xxI2cTransfer(struct I2cCntlr *cntlr, struct I2cMsg *msgs, int16_t count) in Mp1xxI2cTransfer() argument
145 if (cntlr == NULL || cntlr->priv == NULL) { in Mp1xxI2cTransfer()
149 stm32mp1 = (struct Mp1xxI2cCntlr *)cntlr; in Mp1xxI2cTransfer()
175 static int32_t Mp1xxI2cLock(struct I2cCntlr *cntlr) in Mp1xxI2cLock() argument
177 struct Mp1xxI2cCntlr *stm32mp1 = (struct Mp1xxI2cCntlr *)cntlr; in Mp1xxI2cLock()
184 static void Mp1xxI2cUnlock(struct I2cCntlr *cntlr) in Mp1xxI2cUnlock() argument
186 struct Mp1xxI2cCntlr *stm32mp1 = (struct Mp1xxI2cCntlr *)cntlr; in Mp1xxI2cUnlock()
362 stm32mp1->cntlr.priv = (void *)node; in Mp1xxI2cParseAndInit()
363 stm32mp1->cntlr.busId = stm32mp1->bus; in Mp1xxI2cParseAndInit()
364 stm32mp1->cntlr.ops = &g_method; in Mp1xxI2cParseAndInit()
[all …]

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