| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/product/hi3516cv500/ |
| D | hdmi_product_define.c | 72 hi_void drv_hdmi_prod_crg_gate_set(hi_bool enable) in drv_hdmi_prod_crg_gate_set() argument
77 hdmi_reg_ssc_in_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
78 hdmi_reg_ssc_bypass_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
79 hdmi_reg_ctrl_osc_24m_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
80 hdmi_reg_ctrl_cec_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
81 hdmi_reg_ctrl_os_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
82 hdmi_reg_ctrl_as_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
83 hdmi_reg_pxl_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
85 hdmi_reg_hdmirx_phy_tmds_cken_set(enable); in drv_hdmi_prod_crg_gate_set()
91 hi_void drv_hdmi_prod_crg_all_reset_set(hi_bool enable) in drv_hdmi_prod_crg_all_reset_set() argument
[all …]
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| /device/soc/hisilicon/common/platform/mtd/hifmc100/spi_nor/ |
| D | w25qh.c | 25 int32_t HifmcCntlrSpinorEntry4AddrW25qh(struct SpiFlash *spi, int enable) in HifmcCntlrSpinorEntry4AddrW25qh() argument
36 enable = !!enable; // make it 0 or 1 in HifmcCntlrSpinorEntry4AddrW25qh()
37 … HDF_LOGD("%s: start spinor flash 4-byte mode %s", __func__, (enable == 1) ? "enable" : "disbale"); in HifmcCntlrSpinorEntry4AddrW25qh()
46 if ((status & 0x1) == enable) { in HifmcCntlrSpinorEntry4AddrW25qh()
47 HDF_LOGD("%s: 4byte status:%#x, enable:%d", __func__, status, enable); in HifmcCntlrSpinorEntry4AddrW25qh()
51 reg = (enable == 1) ? MTD_SPI_CMD_EN4B : MTD_SPI_CMD_FIRST_RESET_4ADDR; in HifmcCntlrSpinorEntry4AddrW25qh()
63 if (enable == 1) { in HifmcCntlrSpinorEntry4AddrW25qh()
66 if ((status & 0x1) == enable) { in HifmcCntlrSpinorEntry4AddrW25qh()
89 HifmcCntlrSet4AddrMode(cntlr, enable); in HifmcCntlrSpinorEntry4AddrW25qh()
90 HDF_LOGD("%s: end spinor flash 4-byte mode %s", __func__, (enable == 1) ? "enable" : "disbale"); in HifmcCntlrSpinorEntry4AddrW25qh()
[all …]
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| D | hifmc100_spi_nor_ids.c | 94 int enable; in HifmcCntlrSpinorQeEnableDefault() local
101 enable = ((spi->writeCfg.ifType >= MTD_SPI_IF_QUAD) || in HifmcCntlrSpinorQeEnableDefault()
104 if ((!!(config & MTD_SPI_CR_QE_MASK)) == enable) { in HifmcCntlrSpinorQeEnableDefault()
105 HDF_LOGI("%s: qe config:%d, qe enable:%d", __func__, config, enable); in HifmcCntlrSpinorQeEnableDefault()
113 if (enable == 1) { in HifmcCntlrSpinorQeEnableDefault()
138 if ((!!(config & MTD_SPI_CR_QE_MASK)) == enable) { in HifmcCntlrSpinorQeEnableDefault()
139 HDF_LOGI("%s: qe enable:%d set success", __func__, enable); in HifmcCntlrSpinorQeEnableDefault()
142 HDF_LOGE("%s: qe enable:%d set failed", __func__, enable); in HifmcCntlrSpinorQeEnableDefault()
156 static int32_t HifmcCntlrSpinorEntry4AddrDefault(struct SpiFlash *spi, int enable) in HifmcCntlrSpinorEntry4AddrDefault() argument
163 enable = !!enable; // make it 0 or 1 in HifmcCntlrSpinorEntry4AddrDefault()
[all …]
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| D | mx25l.c | 27 int enable; in HifmcCntlrSpinorQeEnableMx25l() local
35 enable = ((spi->writeCfg.ifType >= MTD_SPI_IF_QUAD) || in HifmcCntlrSpinorQeEnableMx25l()
39 if ((!!(status & MTD_SPI_SR_QE_MASK)) == enable) { in HifmcCntlrSpinorQeEnableMx25l()
40 HDF_LOGI("%s: qe status:%d, qe enable:%d", __func__, status, enable); in HifmcCntlrSpinorQeEnableMx25l()
46 if (enable == 1) { in HifmcCntlrSpinorQeEnableMx25l()
70 if ((!!(status & MTD_SPI_SR_QE_MASK)) == enable) { in HifmcCntlrSpinorQeEnableMx25l()
71 HDF_LOGI("%s: qe enable:%d set success", __func__, enable); in HifmcCntlrSpinorQeEnableMx25l()
74 HDF_LOGE("%s: qe enable:%d set failed", __func__, enable); in HifmcCntlrSpinorQeEnableMx25l()
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| /device/soc/hpmicro/sdk/hpm_sdk/drivers/inc/ |
| D | hpm_acmp_drv.h | 137 uint32_t mask, bool enable) in acmp_channel_dma_request_enable() argument
140 | (enable ? mask : 0); in acmp_channel_dma_request_enable()
156 uint32_t mask, bool enable) in acmp_channel_enable_irq() argument
159 | (enable ? mask : 0); in acmp_channel_enable_irq()
171 static inline void acmp_channel_enable_dac(ACMP_Type *ptr, uint8_t ch, bool enable) in acmp_channel_enable_dac() argument
174 | ACMP_CHANNEL_CFG_DACEN_SET(enable); in acmp_channel_enable_dac()
186 static inline void acmp_channel_enable_hpmode(ACMP_Type *ptr, uint8_t ch, bool enable) in acmp_channel_enable_hpmode() argument
189 | ACMP_CHANNEL_CFG_HPMODE_SET(enable); in acmp_channel_enable_hpmode()
214 static inline void acmp_channel_enable_cmp(ACMP_Type *ptr, uint8_t ch, bool enable) in acmp_channel_enable_cmp() argument
217 | ACMP_CHANNEL_CFG_CMPEN_SET(enable); in acmp_channel_enable_cmp()
[all …]
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| D | hpm_sdxc_drv.h | 517 static inline void sdxc_enable_interrupt_status(SDXC_Type *base, uint32_t mask, bool enable) in sdxc_enable_interrupt_status() argument
519 if (enable) { in sdxc_enable_interrupt_status()
532 static inline void sdxc_enable_interrupt_signal(SDXC_Type *base, uint32_t mask, bool enable) in sdxc_enable_interrupt_signal() argument
534 if (enable) { in sdxc_enable_interrupt_signal()
574 static inline void sdxc_interrupt_at_block_gap(SDXC_Type *base, bool enable) in sdxc_interrupt_at_block_gap() argument
576 if (enable) { in sdxc_interrupt_at_block_gap()
588 static inline void sdxc_read_wait_control(SDXC_Type *base, bool enable) in sdxc_read_wait_control() argument
590 if (enable) { in sdxc_read_wait_control()
602 static inline void sdxc_continue_request(SDXC_Type *base, bool enable) in sdxc_continue_request() argument
604 if (enable) { in sdxc_continue_request()
[all …]
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| D | hpm_pmon_drv.h | 24 bool enable) in pmon_enable() argument
28 | PMON_MONITOR_CONTROL_ENABLE_SET(enable); in pmon_enable()
45 static inline void pmon_test_mode_enable(PMON_Type *ptr, bool enable) in pmon_test_mode_enable() argument
48 | PMON_TEST_MODE_DISABLE_SET(!enable); in pmon_test_mode_enable()
51 static inline void pmon_irq_enable(PMON_Type *ptr, uint32_t mask, bool enable) in pmon_irq_enable() argument
53 ptr->IRQ_ENABLE = (ptr->IRQ_ENABLE & ~mask) | (enable ? mask : 0); in pmon_irq_enable()
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| /device/soc/esp/esp32/components/hal/ |
| D | spi_slave_hal.c | 24 … spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, ch… argument
25 … spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, ch… argument
26 …i_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA,… argument
27 …i_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA,… argument
28 …dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA,… argument
29 … spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan… argument
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| D | spi_hal.c | 25 … spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, ch… argument
26 … spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, ch… argument
27 …i_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA,… argument
28 …i_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA,… argument
29 …dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA,… argument
30 … spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan… argument
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| /device/soc/hisilicon/common/hal/middleware/ffmpeg_adapt/ |
| D | configure_llvm | 92 --enable-rpath use rpath to allow installing libraries in paths
98 --enable-gpl allow use of GPL code, the resulting libs
100 --enable-version3 upgrade (L)GPL to version 3 [no]
101 --enable-nonfree allow use of nonfree code, the resulting libs
106 --enable-shared build shared libraries [no]
107 --enable-small optimize for size instead of speed
109 --enable-gray enable full grayscale support (slower color)
135 --enable-avresample enable libavresample build (deprecated) [no]
154 --enable-encoder=NAME enable encoder NAME
157 --enable-decoder=NAME enable decoder NAME
[all …]
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| /device/soc/esp/esp32/components/hal/esp32/include/hal/ |
| D | rwdt_ll.h | 145 FORCE_INLINE_ATTR void rwdt_ll_set_edge_intr(rtc_cntl_dev_t *hw, bool enable) in rwdt_ll_set_edge_intr() argument
147 hw->wdt_config0.edge_int_en = (enable) ? 1 : 0; in rwdt_ll_set_edge_intr()
156 FORCE_INLINE_ATTR void rwdt_ll_set_level_intr(rtc_cntl_dev_t *hw, bool enable) in rwdt_ll_set_level_intr() argument
158 hw->wdt_config0.level_int_en = (enable) ? 1 : 0; in rwdt_ll_set_level_intr()
193 FORCE_INLINE_ATTR void rwdt_ll_set_flashboot_en(rtc_cntl_dev_t* hw, bool enable) in rwdt_ll_set_flashboot_en() argument
195 hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0; in rwdt_ll_set_flashboot_en()
204 FORCE_INLINE_ATTR void rwdt_ll_set_procpu_reset_en(rtc_cntl_dev_t* hw, bool enable) in rwdt_ll_set_procpu_reset_en() argument
206 hw->wdt_config0.procpu_reset_en = (enable) ? 1 : 0; in rwdt_ll_set_procpu_reset_en()
215 FORCE_INLINE_ATTR void rwdt_ll_set_appcpu_reset_en(rtc_cntl_dev_t* hw, bool enable) in rwdt_ll_set_appcpu_reset_en() argument
217 hw->wdt_config0.appcpu_reset_en = (enable) ? 1 : 0; in rwdt_ll_set_appcpu_reset_en()
[all …]
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| D | rmt_ll.h | 30 static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) in rmt_ll_enable_drive_clock() argument
32 dev->conf_ch[0].conf0.clk_en = enable; in rmt_ll_enable_drive_clock()
35 static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) in rmt_ll_power_down_mem() argument
37 dev->conf_ch[0].conf0.mem_pd = enable; // Only conf0 register of channel0 has `mem_pd` in rmt_ll_power_down_mem()
45 static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) in rmt_ll_enable_mem_access() argument
47 dev->apb_conf.fifo_mask = enable; in rmt_ll_enable_mem_access()
97 static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) in rmt_ll_rx_enable() argument
99 dev->conf_ch[channel].conf1.rx_en = enable; in rmt_ll_rx_enable()
144 static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) in rmt_ll_tx_enable_pingpong() argument
146 dev->apb_conf.mem_tx_wrap_en = enable; in rmt_ll_tx_enable_pingpong()
[all …]
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| D | dac_ll.h | 79 static inline void dac_ll_rtc_sync_by_adc(bool enable) in dac_ll_rtc_sync_by_adc() argument
81 SENS.sar_meas_ctrl2.sar1_dac_xpd_fsm = enable; in dac_ll_rtc_sync_by_adc()
109 static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable) in dac_ll_cw_set_channel() argument
112 SENS.sar_dac_ctrl2.dac_cw_en1 = enable; in dac_ll_cw_set_channel()
114 SENS.sar_dac_ctrl2.dac_cw_en2 = enable; in dac_ll_cw_set_channel()
190 static inline void dac_ll_digi_enable_dma(bool enable) in dac_ll_digi_enable_dma() argument
192 SENS.sar_dac_ctrl1.dac_dig_force = enable; in dac_ll_digi_enable_dma()
193 SENS.sar_dac_ctrl1.dac_clk_inv = enable; in dac_ll_digi_enable_dma()
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| D | mwdt_ll.h | 143 FORCE_INLINE_ATTR void mwdt_ll_set_edge_intr(timg_dev_t *hw, bool enable) in mwdt_ll_set_edge_intr() argument
145 hw->wdt_config0.edge_int_en = (enable) ? 1 : 0; in mwdt_ll_set_edge_intr()
154 FORCE_INLINE_ATTR void mwdt_ll_set_level_intr(timg_dev_t *hw, bool enable) in mwdt_ll_set_level_intr() argument
156 hw->wdt_config0.level_int_en = (enable) ? 1 : 0; in mwdt_ll_set_level_intr()
191 FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable) in mwdt_ll_set_flashboot_en() argument
193 hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0; in mwdt_ll_set_flashboot_en()
255 FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t* hw, bool enable) in mwdt_ll_set_intr_enable() argument
257 hw->int_ena.wdt = (enable) ? 1 : 0; in mwdt_ll_set_intr_enable()
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/driver/sys_ctrl/ |
| D | sys_touch_driver.c | 19 uint32_t sys_drv_touch_power_down(uint32_t enable) in sys_drv_touch_power_down() argument
23 sys_hal_touch_power_down(enable); in sys_drv_touch_power_down()
37 uint32_t sys_drv_touch_scan_mode_enable(uint32_t enable) in sys_drv_touch_scan_mode_enable() argument
41 sys_hal_touch_scan_mode_enable(enable); in sys_drv_touch_scan_mode_enable()
64 uint32_t sys_drv_touch_calib_enable(uint32_t enable) in sys_drv_touch_calib_enable() argument
68 sys_hal_touch_calib_enable(enable); in sys_drv_touch_calib_enable()
82 uint32_t sys_drv_touch_manul_mode_enable(uint32_t enable) in sys_drv_touch_manul_mode_enable() argument
86 sys_hal_touch_manul_mode_enable(enable); in sys_drv_touch_manul_mode_enable()
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/ |
| D | hdmi_hal_ctrl.c | 281 static hi_void ctrl_audio_mute_set(hi_bool enable) in ctrl_audio_mute_set() argument
283 hdmi_reg_aud_mute_en_set(enable); in ctrl_audio_mute_set()
295 static hi_void ctrl_audio_i2s_enable_set(hi_bool enable) in ctrl_audio_i2s_enable_set() argument
298 audio_i2s_enable = enable ? HDMI_AUDIO_I2S_SD_ALL : HDMI_AUDIO_I2S_SD_NONE; in ctrl_audio_i2s_enable_set()
457 static hi_s32 ctrl_avmute_get(hi_bool *enable) in ctrl_avmute_get() argument
459 *enable = HI_FALSE; in ctrl_avmute_get()
463 *enable = HI_TRUE; in ctrl_avmute_get()
505 static hi_void ctrl_video_path_dither_set(hi_bool enable, hdmi_video_dither dither_mode) in ctrl_video_path_dither_set() argument
507 hdmi_reg_dither_rnd_bypass_set((!enable)); in ctrl_video_path_dither_set()
540 static hi_void ctrl_video_color_ycbcr422_set(hi_bool enable) in ctrl_video_color_ycbcr422_set() argument
[all …]
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/ |
| D | mali_kbase_hwcnt_legacy.c | 46 …egacy_client_create(struct kbase_hwcnt_virtualizer *hvirt, struct kbase_ioctl_hwcnt_enable *enable, in kbase_hwcnt_legacy_client_create() argument
54 if (!hvirt || !enable || !enable->dump_buffer || !out_hlcli) { in kbase_hwcnt_legacy_client_create()
65 hlcli->user_dump_buf = (void __user *)(uintptr_t)enable->dump_buffer; in kbase_hwcnt_legacy_client_create()
73 phys_em.fe_bm = enable->fe_bm; in kbase_hwcnt_legacy_client_create()
74 phys_em.shader_bm = enable->shader_bm; in kbase_hwcnt_legacy_client_create()
75 phys_em.tiler_bm = enable->tiler_bm; in kbase_hwcnt_legacy_client_create()
76 phys_em.mmu_l2_bm = enable->mmu_l2_bm; in kbase_hwcnt_legacy_client_create()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/clk/ |
| D | ccu_gate.h | 14 u32 enable; member
23 .enable = _gate, \
38 .enable = _gate, \
53 .enable = _gate, \
67 .enable = _gate, \
79 .enable = _gate, \
91 .enable = _gate, \
107 .enable = _gate, \
119 .enable = _gate, \
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| /device/soc/rockchip/common/sdk_linux/drivers/power/supply/ |
| D | Kconfig | 5 Say Y here to enable power supply class support. This allows
15 Say Y here to enable debugging messages for power supply class
36 Say Y here to enable generic power driver for PDAs and phones with
44 Say Y here to enable support APM status emulation using
51 Say Y here to enable support for the generic battery driver
58 Say Y here to enable support for the battery charger in the Maxim
65 Say Y here to enable support for the backup battery charger
72 Say Y here to enable support for the power management unit
79 Say Y here to enable support for the power management unit
91 Say Y here to enable battery monitor for Marvell 88PM860x chip.
[all …]
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| /device/soc/winnermicro/wm800/board/include/driver/ |
| D | wm_lcd.h | 104 bool enable; member
206 #define TLS_LCD_CLK_ENABLE(enable) \ argument
208 tls_bitband_write(HR_CLK_BASE_ADDR, HR_CLK_LCD_GATE_Pos, enable); \
216 #define TLS_LCD_ENABLE(enable) \ argument
218 tls_bitband_write(HR_LCD_CR, LCD_CR_EN_Pos, enable); \
226 #define TLS_LCD_POWERDOWM(enable) \ argument
228 tls_bitband_write(HR_LCD_CR, LCD_CR_PD_Pos, enable); \
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| /device/soc/rockchip/rk3588/kernel/net/rfkill/ |
| D | rfkill-bt.c | 169 (irq->gpio.enable == GPIO_ACTIVE_LOW) ? in rfkill_rk_setup_wake_irq()
200 gpio_direction_output(wake->io, sleep ? !wake->enable : wake->enable); in rfkill_rk_sleep_bt_internal()
209 gpio_direction_output(wake->io, wake->enable); in rfkill_rk_sleep_bt_internal()
211 gpio_direction_output(wake->io, !wake->enable); in rfkill_rk_sleep_bt_internal()
319 if (gpio_get_value(poweron->io) == !poweron->enable) { in rfkill_rk_set_power()
321 !poweron->enable); in rfkill_rk_set_power()
324 poweron->enable); in rfkill_rk_set_power()
332 if (gpio_get_value(reset->io) == !reset->enable) { in rfkill_rk_set_power()
334 !reset->enable); in rfkill_rk_set_power()
336 gpio_direction_output(reset->io, reset->enable); in rfkill_rk_set_power()
[all …]
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| /device/board/isoftstone/yangfan/kernel/src/_net/ |
| D | rfkill-bt.c | 169 (irq->gpio.enable == GPIO_ACTIVE_LOW) ? in rfkill_rk_setup_wake_irq()
200 gpio_direction_output(wake->io, sleep ? !wake->enable : wake->enable); in rfkill_rk_sleep_bt_internal()
209 gpio_direction_output(wake->io, wake->enable); in rfkill_rk_sleep_bt_internal()
211 gpio_direction_output(wake->io, !wake->enable); in rfkill_rk_sleep_bt_internal()
320 if (gpio_get_value(poweron->io) == !poweron->enable) { in rfkill_rk_set_power()
322 !poweron->enable); in rfkill_rk_set_power()
325 poweron->enable); in rfkill_rk_set_power()
333 if (gpio_get_value(reset->io) == !reset->enable) { in rfkill_rk_set_power()
335 !reset->enable); in rfkill_rk_set_power()
337 gpio_direction_output(reset->io, reset->enable); in rfkill_rk_set_power()
[all …]
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| /device/soc/rockchip/common/vendor/drivers/net/ |
| D | rfkill-bt.c | 162 … (irq->gpio.enable == GPIO_ACTIVE_LOW) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING, irq->name, in rfkill_rk_setup_wake_irq()
192 gpio_direction_output(wake->io, sleep ? !wake->enable : wake->enable); in rfkill_rk_sleep_bt_internal()
200 gpio_direction_output(wake->io, wake->enable); in rfkill_rk_sleep_bt_internal()
202 gpio_direction_output(wake->io, !wake->enable); in rfkill_rk_sleep_bt_internal()
308 if (gpio_get_value(poweron->io) == !poweron->enable) { in rfkill_rk_set_power()
309 gpio_direction_output(poweron->io, !poweron->enable); in rfkill_rk_set_power()
311 gpio_direction_output(poweron->io, poweron->enable); in rfkill_rk_set_power()
320 if (gpio_get_value(reset->io) == !reset->enable) { in rfkill_rk_set_power()
321 gpio_direction_output(reset->io, !reset->enable); in rfkill_rk_set_power()
323 gpio_direction_output(reset->io, reset->enable); in rfkill_rk_set_power()
[all …]
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| /device/soc/rockchip/common/vendor/drivers/rockchip/ |
| D | Kconfig | 27 Say y here to enable Rockchip cpuinfo support.
51 Say y here to enable support io domains on Rockchip SoCs. It is
59 Say y here to enable rockchip IPA.
69 Say y here to enable rockchip OPP support.
76 Say y here to enable power domain support.
86 Say y here to enable pvtm support.
100 Say y here to enable rockchip system monitor support.
105 Say y here to enable rockchip vendor storage support.
111 Say y here to enable rockchip mmc vendor storage support.
117 Say y here to enable rockchip flash vendor storage support.
[all …]
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/panel/ |
| D | Kconfig | 27 Say Y here if you want to enable support for the ASUS TMP5P5
37 Say Y here if you want to enable support for Boe Himax8279d
78 Say Y here if you want to enable support for the Elida
88 Say Y here if you want to enable support for the Feixin K101 IM2BA02
97 Say Y if you want to enable support for panels based on the
105 Say Y here if you want to enable support for Ilitek IL9322
114 Say Y if you want to enable support for panels based on the
123 Say Y here if you want to enable support for Innolux P079ZCA
134 Say Y here if you want to enable support for JDI DSI video mode
145 Say Y here if you want to enable support for Kingdisplay kd097d04
[all …]
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