| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/soc/common/hal/include/ |
| D | icu_hal.h | 30 bk_err_t icu_hal_init(icu_hal_t *hal);
34 #define icu_hal_enable_fiq(hal) icu_ll_enable_fiq((hal)->hw) argument
35 #define icu_hal_disable_fiq(hal) icu_ll_disable_fiq((hal)->hw) argument
37 #define icu_hal_enable_irq(hal) icu_ll_enable_irq((hal)->hw) argument
38 #define icu_hal_disable_irq(hal) icu_ll_disable_irq((hal)->hw) argument
40 #define icu_hal_get_global_int_status(hal) icu_ll_get_int_status((hal)->hw) argument
41 #define icu_hal_clear_global_int_status(hal, status) icu_ll_clear_int_status((hal)->hw,status) argument
42 #define icu_hal_get_irq_int_status(hal) icu_ll_get_irq_int_status((hal)->hw) argument
43 #define icu_hal_clear_irq_int_status(hal, status) icu_ll_clear_irq_int_status((hal)->hw,status) argument
44 #define icu_hal_get_fiq_int_status(hal) icu_ll_get_fiq_int_status((hal)->hw) argument
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| D | i2c_hal.h | 30 #define i2c_hal_set_pin(hal) i2c_ll_set_pin(&(hal)->hw, (hal)->id) argument
31 #define i2c_hal_enable(hal) i2c_ll_enable(&(hal)->hw, (hal)->id) argument
32 #define i2c_hal_disable(hal) i2c_ll_disable(&(hal)->hw, (hal)->id) argument
33 #define i2c_hal_enable_start(hal) i2c_ll_enable_start(&(hal)->hw, (hal)->id) argument
34 #define i2c_hal_disable_start(hal) i2c_ll_disable_start(&(hal)->hw, (hal)->id) argument
35 #define i2c_hal_is_start(hal) i2c_ll_is_start(&(hal)->hw, (hal)->id) argument
36 #define i2c_hal_is_start_triggered(hal, int_status) i2c_ll_is_start_triggered(&(hal)->hw, (hal)->id… argument
37 #define i2c_hal_enable_stop(hal) i2c_ll_enable_stop(&(hal)->hw, (hal)->id) argument
38 #define i2c_hal_disable_stop(hal) i2c_ll_disable_stop(&(hal)->hw, (hal)->id) argument
39 #define i2c_hal_is_stop_triggered(hal, int_status) i2c_ll_is_stop_triggered(&(hal)->hw, (hal)->id, … argument
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| D | sdio_host_hal.h | 37 #define sdio_host_hal_reset_config_to_default(hal) sdio_host_ll_reset_config_to_default((hal)->hw) argument
38 #define sdio_host_hal_set_clk_freq(hal, clk_freq) sdio_host_ll_set_clk_freq((hal)->hw, clk_freq) argument
39 #define sdio_host_hal_set_bus_width(hal, bus_width) sdio_host_ll_set_bus_width((hal)->hw, bus_width) argument
40 #define sdio_host_hal_set_cmd_index(hal, cmd_index) sdio_host_ll_set_cmd_index((hal)->hw, cmd_index) argument
41 #define sdio_host_hal_set_send_cmd_argument(hal, cmd_argument) sdio_host_ll_set_send_cmd_argument((… argument
42 #define sdio_host_hal_set_cmd_rsp_timeout(hal, rsp_timeout) sdio_host_ll_set_cmd_rsp_timeout((hal)-… argument
43 #define sdio_host_hal_set_cmd_rsp(hal, is_need_rsp) sdio_host_ll_set_cmd_rsp((hal)->hw, is_need_rsp) argument
44 #define sdio_host_hal_set_cmd_long_rsp(hal, is_long_rsp) sdio_host_ll_set_cmd_long_rsp((hal)->hw, i… argument
45 #define sdio_host_hal_set_cmd_crc_check(hal, is_need_crc_check) sdio_host_ll_set_cmd_crc_check((hal… argument
46 #define sdio_host_hal_start_send_command(hal) sdio_host_ll_start_send_cmd((hal)->hw) argument
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| D | spi_hal.h | 32 #define spi_hal_set_role(hal, role) spi_ll_set_role((hal)->hw, role) argument
33 #define spi_hal_set_bit_width(hal, bit_width) spi_ll_set_bit_width((hal)->hw, bit_width) argument
34 #define spi_hal_set_wire_mode(hal, wire_mode) spi_ll_set_wire_mode((hal)->hw, wire_mode) argument
35 #define spi_hal_set_first_bit(hal, first_bit) spi_ll_set_first_bit((hal)->hw, first_bit) argument
36 #define spi_hal_set_cpol(hal, cpol) spi_ll_set_cpol((hal)->hw, cpol) argument
37 #define spi_hal_set_cpha(hal, cpha) spi_ll_set_cpha((hal)->hw, cpha) argument
38 #define spi_hal_is_master(hal) spi_ll_is_role_master((hal)->hw) argument
39 #define spi_hal_is_slave(hal) spi_ll_is_role_slave((hal)->hw) argument
40 #define spi_hal_get_tx_fifo_int_level(hal) spi_ll_get_tx_fifo_int_level((hal)->hw) argument
41 #define spi_hal_get_rx_fifo_int_level(hal) spi_ll_get_rx_fifo_int_level((hal)->hw) argument
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| D | clock_hal.h | 26 #define clock_hal_set_dco_1_div(hal) clock_ll_set_dco_clk_1_div((hal)->hw) argument
27 #define clock_hal_set_dco_2_div(hal) clock_ll_set_dco_clk_2_div((hal)->hw) argument
28 #define clock_hal_set_dco_4_div(hal) clock_ll_set_dco_clk_4_div((hal)->hw) argument
29 #define clock_hal_set_dco_8_div(hal) clock_ll_set_dco_clk_8_div((hal)->hw) argument
31 #define clock_hal_set_26m_1_div(hal) clock_ll_set_26m_clk_1_div((hal)->hw) argument
32 #define clock_hal_set_26m_2_div(hal) clock_ll_set_26m_clk_2_div((hal)->hw) argument
33 #define clock_hal_set_26m_4_div(hal) clock_ll_set_26m_clk_4_div((hal)->hw) argument
34 #define clock_hal_set_26m_8_div(hal) clock_ll_set_26m_clk_8_div((hal)->hw) argument
39 #define clock_hal_uart_set_clk_26m(hal, id) clock_ll_set_uart_clk_26m((hal)->hw, id) argument
40 #define clock_hal_uart_set_clk_dco(hal, id) clock_ll_set_uart_clk_dco((hal)->hw, id) argument
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| D | power_hal.h | 26 #define power_hal_uart_pwr_up(hal, id) power_ll_pwr_up_uart((hal)->hw, (id)) argument
27 #define power_hal_uart_pwr_down(hal, id) power_ll_pwr_down_uart((hal)->hw, (id)) argument
29 #define power_hal_i2c_pwr_up(hal, id) power_ll_pwr_up_i2c((hal)->hw, id) argument
30 #define power_hal_i2c_pwr_down(hal, id) power_ll_pwr_down_i2c((hal)->hw, id) argument
32 #define power_hal_irda_pwr_up(hal) power_ll_pwr_up_irda((hal)->hw) argument
33 #define power_hal_irda_pwr_down(hal) power_ll_pwr_down_irda((hal)->hw) argument
35 #define power_hal_i2s_pcm_pwr_up(hal) power_ll_pwr_up_i2s_pcm((hal)->hw) argument
36 #define power_hal_i2s_pcm_pwr_down(hal) power_ll_pwr_down_i2s_pcm((hal)->hw) argument
38 #define power_hal_pwr_up_spi(hal, id) power_ll_pwr_up_spi((hal)->hw, id) argument
39 #define power_hal_pwr_down_spi(hal, id) power_ll_pwr_down_spi((hal)->hw, id) argument
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| D | adc_hal.h | 33 #define adc_hal_set_sleep_mode(hal) adc_ll_set_sleep_mode((hal)->hw) argument
34 #define adc_hal_set_single_step_mode(hal) adc_ll_set_single_step_mode((hal)->hw) argument
35 #define adc_hal_set_software_control_mode(hal) adc_ll_set_software_control_mode((hal)->hw) argument
36 #define adc_hal_get_mode(hal) adc_ll_get_adc_mode((hal)->hw) argument
37 #define adc_hal_set_continuous_mode(hal) adc_ll_set_continuous_mode((hal)->hw) argument
38 #define adc_hal_enbale(hal) adc_ll_enable((hal)->hw) argument
39 #define adc_hal_disbale(hal) adc_ll_disable((hal)->hw) argument
40 #define adc_hal_sel_channel(hal, id) adc_ll_sel_channel((hal)->hw, id) argument
41 #define adc_hal_wait_4_cycle(hal) adc_ll_wait_4_cycle((hal)->hw) argument
42 #define adc_hal_wait_8_cycle(hal) adc_ll_wait_8_cycle((hal)->hw) argument
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| D | uart_hal.h | 35 #define uart_hal_enable_tx_interrupt(hal, id) uart_ll_enable_tx_interrupt((hal)->hw, id) argument
36 #define uart_hal_disable_tx_interrupt(hal, id) uart_ll_disable_tx_interrupt((hal)->hw, id) argument
37 #define uart_hal_enable_rx_interrupt(hal, id) uart_ll_enable_rx_interrupt((hal)->hw, id) argument
38 #define uart_hal_disable_rx_interrupt(hal, id) uart_ll_disable_rx_interrupt((hal)->hw, id) argument
39 #define uart_hal_get_interrupt_status(hal, id) uart_ll_get_interrupt_status((hal)->hw, id) argument
40 #define uart_hal_clear_interrupt_status(hal, id, status) uart_ll_clear_interrupt_status((hal)->hw, … argument
41 #define uart_hal_clear_id_interrupt_status(hal, id) uart_ll_clear_id_interrupt_status((hal)->hw, id) argument
42 #define uart_hal_clear_id_tx_interrupt_status(hal, id) uart_ll_clear_id_tx_interrupt_status((hal)->… argument
43 #define uart_hal_clear_id_rx_interrupt_status(hal, id) uart_ll_clear_id_rx_interrupt_status((hal)->… argument
45 #define uart_hal_get_int_enable_status(hal, id) uart_ll_get_int_enable_status((hal)->hw, id) argument
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| D | dma_hal.h | 31 …efine dma_hal_clear_half_finish_interrupt_status(hal, id) dma_ll_clear_half_finish_interrupt_statu… argument
32 #define dma_hal_clear_finish_interrupt_status(hal, id) dma_ll_clear_finish_interrupt_status((hal)->… argument
33 …efine dma_hal_is_half_finish_interrupt_triggered(hal, id) dma_ll_is_half_finish_interrupt_triggere… argument
34 #define dma_hal_is_finish_interrupt_triggered(hal, id) dma_ll_is_finish_interrupt_triggered((hal)->… argument
35 #define dma_hal_enable_finish_interrupt(hal, id) dma_ll_enable_finish_interrupt((hal)->hw, id) argument
36 #define dma_hal_disable_finish_interrupt(hal, id) dma_ll_disable_finish_interrupt((hal)->hw, id) argument
37 #define dma_hal_enable_half_finish_interrupt(hal, id) dma_ll_enable_half_finish_interrupt((hal)->hw… argument
38 #define dma_hal_disable_half_finish_interrupt(hal, id) dma_ll_disable_half_finish_interrupt((hal)->… argument
40 #define dma_hal_reset_config_to_default(hal, id) dma_ll_reset_config_to_default((hal)->hw, (id)) argument
41 #define dma_hal_is_id_started(hal, id) dma_ll_is_id_started((hal)->hw, (id)) argument
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| D | jpeg_hal.h | 39 #define jpeg_hal_enable_end_yuv_int(hal) jpeg_ll_enable_end_yuv_int((hal)->hw) argument
40 #define jpeg_hal_disable_end_yuv_int(hal) jpeg_ll_disable_end_yuv_int((hal)->hw) argument
41 #define jpeg_hal_enable_head_output_int(hal) jpeg_ll_enable_head_output_int((hal)->hw) argument
42 #define jpeg_hal_disable_head_output_int(hal) jpeg_ll_disable_head_output_int((hal)->hw) argument
43 #define jpeg_hal_enable_start_frame_int(hal) jpeg_ll_enable_start_frame_int((hal)->hw) argument
44 #define jpeg_hal_disable_start_frame_int(hal) jpeg_ll_disable_start_frame_int((hal)->hw) argument
45 #define jpeg_hal_enable_end_frame_int(hal) jpeg_ll_enable_end_frame_int((hal)->hw) argument
46 #define jpeg_hal_disable_end_frame_int(hal) jpeg_ll_disable_end_frame_int((hal)->hw) argument
47 #define jpeg_hal_enable_vsync_negedge_int(hal) jpeg_ll_enable_vsync_negedge_int((hal)->hw) argument
48 #define jpeg_hal_disable_vsync_negedge_int(hal) jpeg_ll_disable_vsync_negedge_int((hal)->hw) argument
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/soc/common/hal/ |
| D | aon_rtc_hal.c | 19 void aon_rtc_hal_enable(aon_rtc_hal_t *hal) in aon_rtc_hal_enable() argument
21 hal->hw = (aon_rtc_hw_t *)AON_RTC_LL_REG_BASE(hal->id); in aon_rtc_hal_enable()
22 aon_rtc_ll_enable(hal->hw); in aon_rtc_hal_enable()
25 void aon_rtc_hal_disable(aon_rtc_hal_t *hal) in aon_rtc_hal_disable() argument
27 hal->hw = (aon_rtc_hw_t *)AON_RTC_LL_REG_BASE(hal->id); in aon_rtc_hal_disable()
28 aon_rtc_ll_disable(hal->hw); in aon_rtc_hal_disable()
31 bool aon_rtc_hal_is_enable(aon_rtc_hal_t *hal) in aon_rtc_hal_is_enable() argument
33 hal->hw = (aon_rtc_hw_t *)AON_RTC_LL_REG_BASE(hal->id); in aon_rtc_hal_is_enable()
34 return aon_rtc_ll_is_enable(hal->hw); in aon_rtc_hal_is_enable()
37 void aon_rtc_hal_stop_counter(aon_rtc_hal_t *hal) in aon_rtc_hal_stop_counter() argument
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| D | jpeg_hal.c | 37 bk_err_t jpeg_hal_init(jpeg_hal_t *hal) in jpeg_hal_init() argument
39 hal->hw = (jpeg_hw_t *)JPEG_LL_REG_BASE(hal->id); in jpeg_hal_init()
40 jpeg_ll_init(hal->hw); in jpeg_hal_init()
44 static void jpeg_hal_set_target_bitrate(jpeg_hal_t *hal, uint32_t x_pixel) in jpeg_hal_set_target_bitrate() argument
48 jpeg_ll_set_target_high_byte(hal->hw, JPEG_BITRATE_MAX_SIZE_320_240); in jpeg_hal_set_target_bitrate()
49 jpeg_ll_set_target_low_byte(hal->hw, JPEG_BITRATE_MIN_SIZE_320_240); in jpeg_hal_set_target_bitrate()
52 jpeg_ll_set_target_high_byte(hal->hw, JPEG_BITRATE_MAX_SIZE_640_480); in jpeg_hal_set_target_bitrate()
53 jpeg_ll_set_target_low_byte(hal->hw, JPEG_BITRATE_MIN_SIZE_640_480); in jpeg_hal_set_target_bitrate()
58 jpeg_ll_set_target_high_byte(hal->hw, JPEG_BITRATE_MAX_SIZE_1280_720); in jpeg_hal_set_target_bitrate()
59 jpeg_ll_set_target_low_byte(hal->hw, JPEG_BITRATE_MIN_SIZE_1280_720); in jpeg_hal_set_target_bitrate()
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/driver/include/bk_private/ |
| D | icu_driver.h | 22 icu_hal_t hal; member
34 #define icu_enable_fiq() icu_hal_enable_fiq(&s_icu.hal)
35 #define icu_disable_fiq() icu_hal_disable_fiq(&s_icu.hal)
36 #define icu_enable_irq() icu_hal_enable_irq(&s_icu.hal)
37 #define icu_disable_irq() icu_hal_disable_irq(&s_icu.hal)
48 #define icu_clear_global_int_status(status) icu_hal_clear_global_int_status(&s_icu.hal, status)
49 #define icu_clear_irq_int_status(status) icu_hal_clear_irq_int_status(&s_icu.hal, status)
50 #define icu_clear_fiq_int_status(status) icu_hal_clear_fiq_int_status(&s_icu.hal, status)
51 #define icu_disable_all_interrupt() icu_hal_disable_all_interrupt(&s_icu.hal);
52 #define icu_enable_interrupt(index) icu_hal_enable_interrupt(&s_icu.hal, index);
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| /device/soc/esp/esp32/components/hal/ |
| D | wdt_hal_iram.c | 22 void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescaler, bool enable_intr) in wdt_hal_init() argument
25 memset(hal, 0, sizeof(wdt_hal_context_t)); in wdt_hal_init()
27 hal->mwdt_dev = &TIMERG0; in wdt_hal_init()
29 hal->mwdt_dev = &TIMERG1; in wdt_hal_init()
31 hal->rwdt_dev = &RTCCNTL; in wdt_hal_init()
33 hal->inst = wdt_inst; in wdt_hal_init()
35 if (hal->inst == WDT_RWDT) { in wdt_hal_init()
37 rwdt_ll_write_protect_disable(hal->rwdt_dev); in wdt_hal_init()
39 rwdt_ll_disable(hal->rwdt_dev); in wdt_hal_init()
40 rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE0); in wdt_hal_init()
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| D | spi_slave_hd_hal.c | 52 static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t *hal) in s_spi_slave_hd_hal_dma_init_config() argument
54 spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1); in s_spi_slave_hd_hal_dma_init_config()
55 spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1); in s_spi_slave_hd_hal_dma_init_config()
56 spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1); in s_spi_slave_hd_hal_dma_init_config()
57 spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan, 1); in s_spi_slave_hd_hal_dma_init_config()
58 spi_dma_ll_enable_out_auto_wrback(hal->dma_out, hal->tx_dma_chan, 1); in s_spi_slave_hd_hal_dma_init_config()
59 spi_dma_ll_set_out_eof_generation(hal->dma_out, hal->tx_dma_chan, 1); in s_spi_slave_hd_hal_dma_init_config()
62 void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_co… in spi_slave_hd_hal_init() argument
65 hal->dev = hw; in spi_slave_hd_hal_init()
66 hal->dma_in = hal_config->dma_in; in spi_slave_hd_hal_init()
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| D | i2c_hal.c | 17 void i2c_hal_txfifo_rst(i2c_hal_context_t *hal) in i2c_hal_txfifo_rst() argument
19 i2c_ll_txfifo_rst(hal->dev); in i2c_hal_txfifo_rst()
22 void i2c_hal_rxfifo_rst(i2c_hal_context_t *hal) in i2c_hal_rxfifo_rst() argument
24 i2c_ll_rxfifo_rst(hal->dev); in i2c_hal_rxfifo_rst()
27 void i2c_hal_set_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mo… in i2c_hal_set_data_mode() argument
29 i2c_ll_set_data_mode(hal->dev, tx_mode, rx_mode); in i2c_hal_set_data_mode()
32 void i2c_hal_get_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_… in i2c_hal_get_data_mode() argument
34 i2c_ll_get_data_mode(hal->dev, tx_mode, rx_mode); in i2c_hal_get_data_mode()
37 void i2c_hal_set_filter(i2c_hal_context_t *hal, uint8_t filter_num) in i2c_hal_set_filter() argument
39 i2c_ll_set_filter(hal->dev, filter_num); in i2c_hal_set_filter()
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| D | i2s_hal.c | 24 void i2s_hal_set_tx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_sample_t bits) in i2s_hal_set_tx_mode() argument
27 i2s_ll_set_tx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1); in i2s_hal_set_tx_mode()
29 i2s_ll_set_tx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 2 : 3); in i2s_hal_set_tx_mode()
31 i2s_ll_set_tx_chan_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1); in i2s_hal_set_tx_mode()
33 i2s_ll_set_tx_dma_equal(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1); in i2s_hal_set_tx_mode()
37 void i2s_hal_set_rx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_sample_t bits) in i2s_hal_set_rx_mode() argument
40 i2s_ll_set_rx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1); in i2s_hal_set_rx_mode()
42 i2s_ll_set_rx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 2 : 3); in i2s_hal_set_rx_mode()
44 i2s_ll_set_rx_chan_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1); in i2s_hal_set_rx_mode()
46 i2s_ll_set_rx_dma_equal(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1); in i2s_hal_set_rx_mode()
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| D | spi_slave_hal_iram.c | 36 bool spi_slave_hal_usr_is_done(spi_slave_hal_context_t* hal) in spi_slave_hal_usr_is_done() argument
38 return spi_ll_usr_is_done(hal->hw); in spi_slave_hal_usr_is_done()
41 void spi_slave_hal_user_start(const spi_slave_hal_context_t *hal) in spi_slave_hal_user_start() argument
43 spi_ll_clear_int_stat(hal->hw); //clear int bit in spi_slave_hal_user_start()
44 spi_ll_slave_user_start(hal->hw); in spi_slave_hal_user_start()
47 void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal) in spi_slave_hal_prepare_data() argument
49 if (hal->use_dma) { in spi_slave_hal_prepare_data()
52 if (hal->rx_buffer) { in spi_slave_hal_prepare_data()
53 lldesc_setup_link(hal->dmadesc_rx, hal->rx_buffer, ((hal->bitlen + 7) / 8), true); in spi_slave_hal_prepare_data()
56 spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan); in spi_slave_hal_prepare_data()
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| D | sdio_slave_hal.c | 34 static esp_err_t init_send_queue(sdio_slave_context_t *hal);
158 void sdio_slave_hal_init(sdio_slave_context_t *hal) in sdio_slave_hal_init() argument
160 hal->host = sdio_slave_ll_get_host(0); in sdio_slave_hal_init()
161 hal->slc = sdio_slave_ll_get_slc(0); in sdio_slave_hal_init()
162 hal->hinf = sdio_slave_ll_get_hinf(0); in sdio_slave_hal_init()
163 hal->send_state = STATE_IDLE; in sdio_slave_hal_init()
164 … hal->recv_link_list = (sdio_slave_hal_recv_stailq_t)STAILQ_HEAD_INITIALIZER(hal->recv_link_list); in sdio_slave_hal_init()
166 init_send_queue(hal); in sdio_slave_hal_init()
169 void sdio_slave_hal_hw_init(sdio_slave_context_t *hal) in sdio_slave_hal_hw_init() argument
171 sdio_slave_ll_init(hal->slc); in sdio_slave_hal_hw_init()
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| /device/soc/esp/esp32/components/hal/include/hal/ |
| D | timer_hal.h | 51 void timer_hal_init(timer_hal_context_t *hal, timer_group_t group_num, timer_idx_t timer_num);
60 void timer_hal_get_status_reg_mask_bit(timer_hal_context_t *hal, uint32_t *status_reg, uint32_t *ma…
70 #define timer_hal_set_divider(hal, divider) timer_ll_set_divider((hal)->dev, (hal)->idx, divider) argument
80 #define timer_hal_get_divider(hal, divider) timer_ll_get_divider((hal)->dev, (hal)->idx, divider) argument
90 #define timer_hal_set_counter_value(hal, load_val) timer_ll_set_counter_value((hal)->dev, (hal)->i… argument
100 #define timer_hal_get_counter_value(hal, timer_val) timer_ll_get_counter_value((hal)->dev, (hal)->… argument
110 #define timer_hal_set_counter_increase(hal, increase_en) timer_ll_set_counter_increase((hal)->dev,… argument
122 #define timer_hal_get_counter_increase(hal) timer_ll_get_counter_increase((hal)->dev, (hal)->idx) argument
132 #define timer_hal_set_counter_enable(hal, counter_en) timer_ll_set_counter_enable((hal)->dev, (hal… argument
143 #define timer_hal_get_counter_enable(hal) timer_ll_get_counter_enable((hal)->dev, (hal)->idx) argument
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| D | gpio_hal.h | 56 #define gpio_hal_pullup_en(hal, gpio_num) gpio_ll_pullup_en((hal)->dev, gpio_num) argument
64 #define gpio_hal_pullup_dis(hal, gpio_num) gpio_ll_pullup_dis((hal)->dev, gpio_num) argument
72 #define gpio_hal_pulldown_en(hal, gpio_num) gpio_ll_pulldown_en((hal)->dev, gpio_num) argument
80 #define gpio_hal_pulldown_dis(hal, gpio_num) gpio_ll_pulldown_dis((hal)->dev, gpio_num) argument
89 #define gpio_hal_set_intr_type(hal, gpio_num, intr_type) gpio_ll_set_intr_type((hal)->dev, gpio_num… argument
98 #define gpio_hal_get_intr_status(hal, core_id, status) gpio_ll_get_intr_status((hal)->dev, core_id,… argument
107 #define gpio_hal_get_intr_status_high(hal, core_id, status) gpio_ll_get_intr_status_high((hal)->dev… argument
115 #define gpio_hal_clear_intr_status(hal, mask) gpio_ll_clear_intr_status((hal)->dev, mask) argument
123 #define gpio_hal_clear_intr_status_high(hal, mask) gpio_ll_clear_intr_status_high((hal)->dev, mask) argument
132 void gpio_hal_intr_enable_on_core(gpio_hal_context_t *hal, gpio_num_t gpio_num, uint32_t core_id);
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| D | ledc_hal.h | 45 #define ledc_hal_set_slow_clk_sel(hal, slow_clk_sel) ledc_ll_set_slow_clk_sel((hal)->dev, slow_clk… argument
55 #define ledc_hal_get_slow_clk_sel(hal, slow_clk_sel) ledc_ll_get_slow_clk_sel((hal)->dev, slow_clk… argument
65 #define ledc_hal_ls_timer_update(hal, timer_sel) ledc_ll_ls_timer_update((hal)->dev, (hal)->speed_… argument
75 #define ledc_hal_timer_rst(hal, timer_sel) ledc_ll_timer_rst((hal)->dev, (hal)->speed_mode, timer_… argument
85 #define ledc_hal_timer_pause(hal, timer_sel) ledc_ll_timer_pause((hal)->dev, (hal)->speed_mode, ti… argument
95 #define ledc_hal_timer_resume(hal, timer_sel) ledc_ll_timer_resume((hal)->dev, (hal)->speed_mode, … argument
106 #define ledc_hal_set_clock_divider(hal, timer_sel, clock_divider) ledc_ll_set_clock_divider((hal)-… argument
117 #define ledc_hal_get_clock_divider(hal, timer_sel, clock_divider) ledc_ll_get_clock_divider((hal)-… argument
128 #define ledc_hal_set_clock_source(hal, timer_sel, clk_src) ledc_ll_set_clock_source((hal)->dev, (h… argument
139 #define ledc_hal_get_clock_source(hal, timer_sel, clk_src) ledc_ll_get_clock_source((hal)->dev, (h… argument
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| D | uart_hal.h | 48 #define uart_hal_clr_intsts_mask(hal, mask) uart_ll_clr_intsts_mask((hal)->dev, mask) argument
58 #define uart_hal_disable_intr_mask(hal, mask) uart_ll_disable_intr_mask((hal)->dev, mask) argument
68 #define uart_hal_ena_intr_mask(hal, mask) uart_ll_ena_intr_mask((hal)->dev, mask) argument
77 #define uart_hal_get_intsts_mask(hal) uart_ll_get_intsts_mask((hal)->dev) argument
86 #define uart_hal_get_intr_ena_status(hal) uart_ll_get_intr_ena_status((hal)->dev) argument
97 #define uart_hal_get_at_cmd_char(hal, cmd_char, char_num) uart_ll_get_at_cmd_char((hal)->dev, cmd_… argument
107 #define uart_hal_set_rts(hal, active_level) uart_ll_set_rts_active_level((hal)->dev, active_level) argument
116 #define uart_hal_get_txfifo_len(hal) uart_ll_get_txfifo_len((hal)->dev) argument
125 #define uart_hal_is_tx_idle(hal) uart_ll_is_tx_idle((hal)->dev) argument
135 #define uart_hal_set_reset_core(hal, core_rst_en) uart_ll_set_reset_core((hal)->dev, core_rst_en) argument
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| /device/board/unionman/unionpi_tiger/kernel/drivers/rtl88x2cs/hal/phydm/ |
| D | phydm.mk | 1 EXTRA_CFLAGS += -I$(src)/hal/phydm
3 _PHYDM_FILES := hal/phydm/phydm_debug.o \
4 hal/phydm/phydm_antdiv.o\
5 hal/phydm/phydm_soml.o\
6 hal/phydm/phydm_smt_ant.o\
7 hal/phydm/phydm_antdect.o\
8 hal/phydm/phydm_interface.o\
9 hal/phydm/phydm_phystatus.o\
10 hal/phydm/phydm_hwconfig.o\
11 hal/phydm/phydm.o\
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| D | sd4_phydm_2_kernel.mk | 1 EXTRA_CFLAGS += -I$(src)/hal/phydm
3 _PHYDM_FILES := hal/phydm/phydm_debug.o \
4 hal/phydm/phydm_interface.o\
5 hal/phydm/phydm_phystatus.o\
6 hal/phydm/phydm_hwconfig.o\
7 hal/phydm/phydm.o\
8 hal/phydm/phydm_dig.o\
9 hal/phydm/phydm_rainfo.o\
10 hal/phydm/phydm_adaptivity.o\
11 hal/phydm/phydm_cfotracking.o\
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