1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef ROCKCHIP_MIPI_CSI_TX 7 #define ROCKCHIP_MIPI_CSI_TX 8 9 #define DRIVER_NAME "rockchip-mipi-csi" 10 11 #define CSITX_CONFIG_DONE 0x0000 12 #define m_CONFIG_DONE BIT(0) 13 #define m_CONFIG_DONE_IMD BIT(4) 14 #define m_CONFIG_DONE_MODE BIT(8) 15 #define v_CONFIG_DONE(x) (((x) & 0x1) << 0) 16 #define v_CONFIG_DONE_IMD(x) (((x) & 0x1) << 4) 17 #define v_CONFIG_DONE_MODE(x) (((x) & 0x1) << 8) 18 enum CONFIG_DONE_MODE { 19 FRAME_END_RX_MODE, 20 FRAME_END_TX_MODE 21 }; 22 23 #define CSITX_ENABLE 0x0004 24 #define m_CSITX_EN BIT(0) 25 #define m_CPHY_EN BIT(1) 26 #define m_DPHY_EN BIT(2) 27 #define m_LANE_NUM GENMASK(5, 4) 28 #define m_IDI_48BIT_EN BIT(9) 29 #define v_CSITX_EN(x) (((x) & 0x1) << 0) 30 #define v_CPHY_EN(x) (((x) & 0x1) << 1) 31 #define v_DPHY_EN(x) (((x) & 0x1) << 2) 32 #define v_LANE_NUM(x) (((x) & 0x3) << 4) 33 #define v_IDI_48BIT_EN(x) (((x) & 0x1) << 9) 34 35 #define CSITX_VERSION 0x0008 36 #define CSITX_SYS_CTRL0 0x0010 37 #define m_SOFT_RESET BIT(0) 38 #define v_SOFT_RESET(x) (((x) & 0x1) << 0) 39 40 #define CSITX_SYS_CTRL1 0x0014 41 #define m_BYPASS_SELECT BIT(0) 42 #define v_BYPASS_SELECT(x) (((x) & 0x1) << 0) 43 44 #define CSITX_SYS_CTRL2 0x0018 45 #define m_VSYNC_ENABLE BIT(0) 46 #define m_HSYNC_ENABLE BIT(1) 47 #define m_IDI_WHOLE_FRM_EN BIT(4) 48 #define m_VOP_WHOLE_FRM_EN BIT(5) 49 #define v_VSYNC_ENABLE(x) (((x) & 0x1) << 0) 50 #define v_HSYNC_ENABLE(x) (((x) & 0x1) << 1) 51 #define v_IDI_WHOLE_FRM_EN(x) (((x) & 0x1) << 4) 52 #define v_VOP_WHOLE_FRM_EN(x) (((x) & 0x1) << 5) 53 54 #define CSITX_SYS_CTRL3 0x001c 55 #define m_NON_CONTINUES_MODE_EN BIT(0) 56 #define m_CONT_MODE_CLK_SET BIT(4) 57 #define m_CONT_MODE_CLK_CLR BIT(8) 58 #define v_NON_CONTINUES_MODE_EN(x) (((x) & 0x1) << 0) 59 #define v_CONT_MODE_CLK_SET(x) (((x) & 0x1) << 4) 60 #define v_CONT_MODE_CLK_CLR(x) (((x) & 0x1) << 8) 61 62 #define CSITX_TIMING_CTRL 0x0020 63 #define CSITX_TIMING_VPW_NUM 0x0024 64 #define CSITX_TIMING_VBP_NUM 0x0028 65 #define CSITX_TIMING_VFP_NUM 0x002c 66 #define CSITX_TIMING_HPW_PADDING_NUM 0x0030 67 68 #define CSITX_VOP_PATH_CTRL 0x0040 69 #define m_VOP_PATH_EN BIT(0) 70 #define m_VOP_DT_USERDEFINE_EN BIT(1) 71 #define m_VOP_VC_USERDEFINE_EN BIT(2) 72 #define m_VOP_WC_USERDEFINE_EN BIT(3) 73 #define m_PIXEL_FORMAT GENMASK(7, 4) 74 #define m_VOP_DT_USERDEFINE GENMASK(13, 8) 75 #define m_VOP_VC_USERDEFINE GENMASK(15, 14) 76 #define m_VOP_WC_USERDEFINE GENMASK(31, 16) 77 #define v_VOP_PATH_EN(x) (((x) & 0x1) << 0) 78 #define v_VOP_DT_USERDEFINE_EN(x) (((x) & 0x1) << 1) 79 #define v_VOP_VC_USERDEFINE_EN(x) (((x) & 0x1) << 2) 80 #define v_VOP_WC_USERDEFINE_EN(x) (((x) & 0x1) << 3) 81 #define v_PIXEL_FORMAT(x) (((x) & 0xf) << 4) 82 #define v_VOP_DT_USERDEFINE(x) (((x) & 0x3f) << 8) 83 #define v_VOP_VC_USERDEFINE(x) (((x) & 0x3) << 14) 84 #define v_VOP_WC_USERDEFINE(x) (((x) & 0xffff) << 16) 85 86 #define CSITX_VOP_PATH_PKT_CTRL 0x0050 87 #define m_VOP_LINE_PADDING_EN BIT(4) 88 #define m_VOP_LINE_PADDING_NUM GENMASK(7, 5) 89 #define m_VOP_PKT_PADDING_EN BIT(8) 90 #define m_VOP_WC_ACTIVE GENMASK(31, 16) 91 #define v_VOP_LINE_PADDING_EN(x) (((x) & 0x1) << 4) 92 #define v_VOP_LINE_PADDING_NUM(x) (((x) & 0x7) << 5) 93 #define v_VOP_PKT_PADDING_EN(x) (((x) & 0x1) << 8) 94 #define v_VOP_WC_ACTIVE(x) (((x) & 0xff) << 16) 95 96 #define CSITX_BYPASS_PATH_CTRL 0x0060 97 #define m_BYPASS_PATH_EN BIT(0) 98 #define m_BYPASS_DT_USERDEFINE_EN BIT(1) 99 #define m_BYPASS_VC_USERDEFINE_EN BIT(2) 100 #define m_BYPASS_WC_USERDEFINE_EN BIT(3) 101 #define m_CAM_FORMAT GENMASK(7, 4) 102 #define m_BYPASS_DT_USERDEFINE GENMASK(13, 8) 103 #define m_BYPASS_VC_USERDEFINE GENMASK(15, 14) 104 #define m_BYPASS_WC_USERDEFINE GENMASK(31, 16) 105 #define v_BYPASS_PATH_EN(x) (((x) & 0x1) << 0) 106 #define v_BYPASS_DT_USERDEFINE_EN(x) (((x) & 0x1) << 1) 107 #define v_BYPASS_VC_USERDEFINE_EN(x) (((x) & 0x1) << 2) 108 #define v_BYPASS_WC_USERDEFINE_EN(x) (((x) & 0x1) << 3) 109 #define v_CAM_FORMAT(x) (((x) & 0xf) << 4) 110 #define v_BYPASS_DT_USERDEFINE(x) (((x) & 0x3f) << 8) 111 #define v_BYPASS_VC_USERDEFINE(x) (((x) & 0x3) << 14) 112 #define v_BYPASS_WC_USERDEFINE(x) (((x) & 0xff) << 16) 113 114 #define CSITX_BYPASS_PATH_PKT_CTRL 0x0064 115 #define m_BYPASS_LINE_PADDING_EN BIT(4) 116 #define m_BYPASS_LINE_PADDING_NUM GENMASK(7, 5) 117 #define m_BYPASS_PKT_PADDING_EN BIT(8) 118 #define m_BYPASS_WC_ACTIVE GENMASK(31, 16) 119 #define v_BYPASS_LINE_PADDING_EN(x) (((x) & 0x1) << 4) 120 #define v_BYPASS_LINE_PADDING_NUM(x) (((x) & 0x7) << 5) 121 #define v_BYPASS_PKT_PADDING_EN(x) (((x) & 0x1) << 8) 122 #define v_BYPASS_WC_ACTIVE(x) (((x) & 0xff) << 16) 123 124 #define CSITX_STATUS0 0x0070 125 #define CSITX_STATUS1 0x0074 126 #define m_DPHY_PLL_LOCK BIT(0) 127 #define m_STOPSTATE_CLK BIT(1) 128 #define m_STOPSTATE_LANE GENMASK(7, 4) 129 #define PHY_STOPSTATELANE (m_STOPSTATE_CLK | m_STOPSTATE_LANE) 130 131 #define CSITX_STATUS2 0x0078 132 #define CSITX_LINE_FLAG_NUM 0x007c 133 #define CSITX_INTR_EN 0x0080 134 #define m_INTR_MASK GENMASK(26, 16) 135 #define m_FRM_ST_RX BIT(0 + 16) 136 #define m_FRM_END_RX BIT(1 + 16) 137 #define m_LINE_END_TX BIT(2 + 16) 138 #define m_FRM_ST_TX BIT(3 + 16) 139 #define m_FRM_END_TX BIT(4 + 16) 140 #define m_LINE_END_RX BIT(5 + 16) 141 #define m_LINE_FLAG0 BIT(6 + 16) 142 #define m_LINE_FLAG1 BIT(7 + 16) 143 #define m_STOP_STATE BIT(8 + 16) 144 #define m_PLL_LOCK BIT(9 + 16) 145 #define m_CSITX_IDLE BIT(10 + 16) 146 #define v_FRM_ST_RX(x) (((x) & 0x1) << 0) 147 #define v_FRM_END_RX(x) (((x) & 0x1) << 1) 148 #define v_LINE_END_TX(x) (((x) & 0x1) << 2) 149 #define v_FRM_ST_TX(x) (((x) & 0x1) << 3) 150 #define v_FRM_END_TX(x) (((x) & 0x1) << 4) 151 #define v_LINE_END_RX(x) (((x) & 0x1) << 5) 152 #define v_LINE_FLAG0(x) (((x) & 0x1) << 6) 153 #define v_LINE_FLAG1(x) (((x) & 0x1) << 7) 154 #define v_STOP_STATE(x) (((x) & 0x1) << 8) 155 #define v_PLL_LOCK(x) (((x) & 0x1) << 9) 156 #define v_CSITX_IDLE(x) (((x) & 0x1) << 10) 157 158 #define CSITX_INTR_CLR 0x0084 159 #define CSITX_INTR_STATUS 0x0088 160 #define CSITX_INTR_RAW_STATUS 0x008c 161 162 #define CSITX_ERR_INTR_EN 0x0090 163 #define m_ERR_INTR_EN GENMASK(11, 0) 164 #define m_ERR_INTR_MASK GENMASK(27, 16) 165 #define m_IDI_HDR_FIFO_OVERFLOW BIT(0 + 16) 166 #define m_IDI_HDR_FIFO_UNDERFLOW BIT(1 + 16) 167 #define m_IDI_PLD_FIFO_OVERFLOW BIT(2 + 16) 168 #define m_IDI_PLD_FIFO_UNDERFLOW BIT(3 + 16) 169 #define m_HDR_FIFO_OVERFLOW BIT(4 + 16) 170 #define m_HDR_FIFO_UNDERFLOW BIT(5 + 16) 171 #define m_PLD_FIFO_OVERFLOW BIT(6 + 16) 172 #define m_PLD_FIFO_UNDERFLOW BIT(7 + 16) 173 #define m_OUTBUFFER_OVERFLOW BIT(8 + 16) 174 #define m_OUTBUFFER_UNDERFLOW BIT(9 + 16) 175 #define m_TX_TXREADYHS_OVERFLOW BIT(10 + 16) 176 #define m_TX_TXREADYHS_UNDERFLOW BIT(11 + 16) 177 178 #define CSITX_ERR_INTR_CLR 0x0094 179 #define CSITX_ERR_INTR_STATUS 0x0098 180 #define CSITX_ERR_INTR_RAW_STATUS 0x009c 181 #define CSITX_ULPS_CTRL 0x00a0 182 #define CSITX_LPDT_CTRL 0x00a4 183 #define CSITX_LPDT_DATA 0x00a8 184 #define CSITX_DPHY_CTRL 0x00b0 185 #define m_CSITX_ENABLE_PHY GENMASK(7, 3) 186 #define v_CSITX_ENABLE_PHY(x) (((x) & 0x1f) << 3) 187 #define CSITX_DPHY_PPI_CTRL 0x00b4 188 #define CSITX_DPHY_TEST_CTRL 0x00b8 189 #define CSITX_DPHY_ERROR 0x00bc 190 #define CSITX_DPHY_SCAN_CTRL 0x00c0 191 #define CSITX_DPHY_SCANIN 0x00c4 192 #define CSITX_DPHY_SCANOUT 0x00c8 193 #define CSITX_DPHY_BIST 0x00d0 194 195 #define MIPI_CSI_FMT_RAW8 0x10 196 #define MIPI_CSI_FMT_RAW10 0x11 197 198 #define PHY_STATUS_TIMEOUT_US 10000 199 #define CMD_PKT_STATUS_TIMEOUT_US 20000 200 201 #define RK_CSI_TX_MAX_RESET 5 202 203 enum soc_type { 204 RK1808, 205 }; 206 207 enum csi_path_mode { 208 VOP_PATH, 209 BYPASS_PATH 210 }; 211 212 #define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb)) 213 214 enum grf_reg_fields { 215 DPIUPDATECFG, 216 DPISHUTDN, 217 DPICOLORM, 218 VOPSEL, 219 TURNREQUEST, 220 TURNDISABLE, 221 FORCETXSTOPMODE, 222 FORCERXMODE, 223 ENABLE_N, 224 MASTERSLAVEZ, 225 ENABLECLK, 226 BASEDIR, 227 DPHY_SEL, 228 TXSKEWCALHS, 229 MAX_FIELDS, 230 }; 231 232 struct rockchip_mipi_csi_plat_data { 233 const u32 *csi0_grf_reg_fields; 234 const u32 *csi1_grf_reg_fields; 235 unsigned long max_bit_rate_per_lane; 236 enum soc_type soc_type; 237 const char * const *rsts; 238 int rsts_num; 239 }; 240 241 struct mipi_dphy { 242 /* SNPS PHY */ 243 struct clk *cfg_clk; 244 struct clk *ref_clk; 245 u16 input_div; 246 u16 feedback_div; 247 248 /* Non-SNPS PHY */ 249 struct phy *phy; 250 struct clk *hs_clk; 251 }; 252 253 struct rockchip_mipi_csi { 254 struct drm_encoder encoder; 255 struct drm_connector connector; 256 struct device_node *client; 257 struct mipi_dsi_host dsi_host; 258 struct mipi_dphy dphy; 259 struct drm_panel *panel; 260 struct device *dev; 261 struct regmap *grf; 262 struct reset_control *tx_rsts[RK_CSI_TX_MAX_RESET]; 263 void __iomem *regs; 264 void __iomem *test_code_regs; 265 struct regmap *regmap; 266 u32 *regsbak; 267 u32 regs_len; 268 struct clk *pclk; 269 struct clk *ref_clk; 270 int irq; 271 272 unsigned long mode_flags; 273 unsigned int lane_mbps; /* per lane */ 274 u32 channel; 275 u32 lanes; 276 u32 format; 277 struct drm_display_mode mode; 278 u32 path_mode; /* vop path or bypass path */ 279 struct drm_property *csi_tx_path_property; 280 281 const struct rockchip_mipi_csi_plat_data *pdata; 282 }; 283 284 enum rockchip_mipi_csi_mode { 285 DSI_COMMAND_MODE, 286 DSI_VIDEO_MODE, 287 }; 288 289 #endif 290