1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMRAINFO_H__ 27 #define __PHYDMRAINFO_H__ 28 29 /* 2020.08.05 Fix ARFR bug due to rate_id error for 2.4G VHT mode*/ 30 #define RAINFO_VERSION "8.8" 31 32 #define FORCED_UPDATE_RAMASK_PERIOD 5 33 34 #define H2C_MAX_LENGTH 7 35 36 #define RA_FLOOR_UP_GAP 3 37 #define RA_FLOOR_TABLE_SIZE 7 38 39 #define ACTIVE_TP_THRESHOLD 1 40 #define RA_RETRY_DESCEND_NUM 2 41 #define RA_RETRY_LIMIT_LOW 4 42 #define RA_RETRY_LIMIT_HIGH 32 43 44 #define PHYDM_IS_LEGACY_RATE(rate) ((rate <= ODM_RATE54M) ? true : false) 45 #define PHYDM_IS_CCK_RATE(rate) ((rate <= ODM_RATE11M) ? true : false) 46 47 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 48 #define FIRST_MACID 1 49 #else 50 #define FIRST_MACID 0 51 #endif 52 53 /* @1 ============================================================ 54 * 1 enumrate 55 * 1 ============================================================ 56 */ 57 58 enum phydm_ra_dbg_para { 59 RADBG_PCR_TH_OFFSET = 0, 60 RADBG_RTY_PENALTY = 1, 61 RADBG_N_HIGH = 2, 62 RADBG_N_LOW = 3, 63 RADBG_TRATE_UP_TABLE = 4, 64 RADBG_TRATE_DOWN_TABLE = 5, 65 RADBG_TRYING_NECESSARY = 6, 66 RADBG_TDROPING_NECESSARY = 7, 67 RADBG_RATE_UP_RTY_RATIO = 8, 68 RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ 69 70 RADBG_DEBUG_MONITOR1 = 0xc, 71 RADBG_DEBUG_MONITOR2 = 0xd, 72 RADBG_DEBUG_MONITOR3 = 0xe, 73 RADBG_DEBUG_MONITOR4 = 0xf, 74 RADBG_DEBUG_MONITOR5 = 0x10, 75 NUM_RA_PARA 76 }; 77 78 enum phydm_wireless_mode { 79 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, 80 PHYDM_WIRELESS_MODE_A = 0x01, 81 PHYDM_WIRELESS_MODE_B = 0x02, 82 PHYDM_WIRELESS_MODE_G = 0x04, 83 PHYDM_WIRELESS_MODE_AUTO = 0x08, 84 PHYDM_WIRELESS_MODE_N_24G = 0x10, 85 PHYDM_WIRELESS_MODE_N_5G = 0x20, 86 PHYDM_WIRELESS_MODE_AC_5G = 0x40, 87 PHYDM_WIRELESS_MODE_AC_24G = 0x80, 88 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, 89 PHYDM_WIRELESS_MODE_MAX = 0x800, 90 PHYDM_WIRELESS_MODE_ALL = 0xFFFF 91 }; 92 93 enum phydm_rateid_idx { 94 PHYDM_BGN_40M_2SS = 0, 95 PHYDM_BGN_40M_1SS = 1, 96 PHYDM_BGN_20M_2SS = 2, 97 PHYDM_BGN_20M_1SS = 3, 98 PHYDM_GN_N2SS = 4, 99 PHYDM_GN_N1SS = 5, 100 PHYDM_BG = 6, 101 PHYDM_G = 7, 102 PHYDM_B_20M = 8, 103 PHYDM_ARFR0_AC_2SS = 9, 104 PHYDM_ARFR1_AC_1SS = 10, 105 PHYDM_ARFR2_AC_2G_1SS = 11, 106 PHYDM_ARFR3_AC_2G_2SS = 12, 107 PHYDM_ARFR4_AC_3SS = 13, 108 PHYDM_ARFR5_N_3SS = 14, 109 PHYDM_ARFR7_N_4SS = 15, 110 PHYDM_ARFR6_AC_4SS = 16 111 }; 112 113 /*ARFR4(0x49c/0x4a0) can not be used because FW BT would use.*/ 114 enum phydm_rateid_idx_type_2 { 115 PHYDM_TYPE2_AC_2SS = 9, 116 PHYDM_TYPE2_AC_1SS = 10, 117 PHYDM_TYPE2_MIX_1SS = 11, 118 PHYDM_TYPE2_MIX_2SS = 12, 119 PHYDM_TYPE2_ARFR3_AC_2G_2SS = 16, /*0x494/0x498*/ 120 PHYDM_TYPE2_ARFR5_AC_2G_1SS = 18 /*0x4a4/0x4a8*/ 121 }; 122 123 enum phydm_qam_order { 124 PHYDM_QAM_CCK = 0, 125 PHYDM_QAM_BPSK = 1, 126 PHYDM_QAM_QPSK = 2, 127 PHYDM_QAM_16QAM = 3, 128 PHYDM_QAM_64QAM = 4, 129 PHYDM_QAM_256QAM = 5 130 }; 131 132 #if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */ 133 134 struct _phydm_txstatistic_ { 135 u32 hw_total_tx; 136 u32 hw_tx_success; 137 u32 hw_tx_rty; 138 u32 hw_tx_drop; 139 }; 140 141 /* @1 ============================================================ 142 * 1 structure 143 * 1 ============================================================ 144 */ 145 struct _odm_ra_info_ { 146 u8 rate_id; 147 u32 rate_mask; 148 u32 ra_use_rate; 149 u8 rate_sgi; 150 u8 rssi_sta_ra; 151 u8 pre_rssi_sta_ra; 152 u8 sgi_enable; 153 u8 decision_rate; 154 u8 pre_rate; 155 u8 highest_rate; 156 u8 lowest_rate; 157 u32 nsc_up; 158 u32 nsc_down; 159 u16 RTY[5]; 160 u32 TOTAL; 161 u16 DROP; 162 u8 active; 163 u16 rpt_time; 164 u8 ra_waiting_counter; 165 u8 ra_pending_counter; 166 u8 ra_drop_after_down; 167 #if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */ 168 u8 pt_active; /* on or off */ 169 u8 pt_try_state; /* @0 trying state, 1 for decision state */ 170 u8 pt_stage; /* @0~6 */ 171 u8 pt_stop_count; /* Stop PT counter */ 172 u8 pt_pre_rate; /* @if rate change do PT */ 173 u8 pt_pre_rssi; /* @if RSSI change 5% do PT */ 174 u8 pt_mode_ss; /* @decide whitch rate should do PT */ 175 u8 ra_stage; /* @StageRA, decide how many times RA will be done between PT */ 176 u8 pt_smooth_factor; 177 #endif 178 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) 179 u8 rate_down_counter; 180 u8 rate_up_counter; 181 u8 rate_direction; 182 u8 bounding_type; 183 u8 bounding_counter; 184 u8 bounding_learning_time; 185 u8 rate_down_start_time; 186 #endif 187 }; 188 #endif 189 190 191 struct ra_table { 192 #ifdef MU_EX_MACID 193 u8 mu1_rate[MU_EX_MACID]; 194 #endif 195 u8 highest_client_tx_order; 196 u16 highest_client_tx_rate_order; 197 u8 power_tracking_flag; 198 u8 ra_th_ofst; /*RA_threshold_offset*/ 199 u8 ra_ofst_direc; /*RA_offset_direction*/ 200 u8 up_ramask_cnt; /*@force update_ra_mask counter*/ 201 u8 up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/ 202 u32 rrsr_val_init; /*0x440*/ 203 u32 rrsr_val_curr; /*0x440*/ 204 boolean dynamic_rrsr_en; 205 u8 ra_trigger_mode; /*0: pkt RA, 1: TBTT RA*/ 206 u8 ra_tx_cls_th; /*255: auto, xx: in dB*/ 207 #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ 208 u8 per_rate_retrylimit_20M[PHY_NUM_RATE_IDX]; 209 u8 per_rate_retrylimit_40M[PHY_NUM_RATE_IDX]; 210 u8 retry_descend_num; 211 u8 retrylimit_low; 212 u8 retrylimit_high; 213 #endif 214 u8 ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */ 215 void (*record_ra_info)(void *dm_void, u8 macid, 216 struct cmn_sta_info *sta, u64 ra_mask); 217 u8 ra_mask_rpt_stamp; 218 u8 ra_mask_buf[8]; 219 }; 220 221 struct ra_mask_rpt_trig { 222 u8 ra_mask_rpt_stamp; 223 u8 macid; 224 }; 225 226 struct ra_mask_rpt { 227 u8 ra_mask_rpt_stamp; 228 u8 ra_mask_buf[8]; 229 }; 230 231 /* @1 ============================================================ 232 * 1 Function Prototype 233 * 1 ============================================================ 234 */ 235 boolean phydm_is_cck_rate(void *dm_void, u8 rate); 236 237 boolean phydm_is_ofdm_rate(void *dm_void, u8 rate); 238 239 boolean phydm_is_ht_rate(void *dm_void, u8 rate); 240 241 boolean phydm_is_vht_rate(void *dm_void, u8 rate); 242 243 u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate); 244 245 u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate); 246 247 u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type); 248 249 u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate); 250 251 void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used, 252 char *output, u32 *_out_len); 253 254 void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output, 255 u32 *_out_len); 256 257 void phydm_ra_mask_report_h2c_trigger(void *dm_void, 258 struct ra_mask_rpt_trig *trig_rpt); 259 260 void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt); 261 262 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); 263 264 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component); 265 266 void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size); 267 268 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); 269 270 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx); 271 272 void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val); 273 274 void phydm_ra_info_watchdog(void *dm_void); 275 276 void phydm_rrsr_en(void *dm_void, boolean en_rrsr); 277 278 void phydm_ra_info_init(void *dm_void); 279 280 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc, 281 u8 ra_th_ofst); 282 283 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode); 284 285 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw); 286 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 287 void phydm_update_hal_ra_mask( 288 void *dm_void, 289 u32 wireless_mode, 290 u8 rf_type, 291 u8 BW, 292 u8 mimo_ps_enable, 293 u8 disable_cck_rate, 294 u32 *ratr_bitmap_msb_in, 295 u32 *ratr_bitmap_in, 296 u8 tx_rate_level); 297 #endif 298 299 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 300 u8 phydm_get_plcp(void *dm_void, u16 macid); 301 #endif 302 303 void phydm_refresh_rate_adaptive_mask(void *dm_void); 304 305 u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type); 306 307 u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state); 308 309 void odm_ra_post_action_on_assoc(void *dm); 310 311 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect); 312 313 void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used, 314 char *output, u32 *_out_len); 315 316 u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx); 317 318 void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc); 319 320 void phydm_ra_offline(void *dm_void, u8 macid); 321 322 void phydm_ra_mask_watchdog(void *dm_void); 323 324 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 325 void odm_refresh_basic_rate_mask( 326 void *dm_void); 327 #endif 328 329 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 330 void phydm_ra_mode_selection(void *dm_void, u8 mode); 331 #endif 332 333 #endif /*@#ifndef __PHYDMRAINFO_H__*/ 334