Searched refs:ram (Results 1 – 25 of 31) sorted by relevance
12
| /device/soc/hisilicon/common/platform/hieth-sf/adapter/ |
| D | hieth_phy.c | 44 pstPrivData->ram = (EthRamCfg *)OsalMemCalloc(sizeof(EthRamCfg)); in CreateHiethPrivData()
45 if (pstPrivData->ram == NULL) { in CreateHiethPrivData()
49 pstPrivData->ram->txqInfo = OsalMemCalloc(HIETH_HWQ_TXQ_SIZE * sizeof(struct TxPktInfo)); in CreateHiethPrivData()
50 if (!pstPrivData->ram->txqInfo) { in CreateHiethPrivData()
54 pstPrivData->ram->rxNetbuf = OsalMemCalloc(HIETH_HWQ_RXQ_DEPTH * sizeof(NetBuf *)); in CreateHiethPrivData()
55 if (!pstPrivData->ram->rxNetbuf) { in CreateHiethPrivData()
60 pstPrivData->ram->pbufInfo = OsalMemCalloc(HIETH_HWQ_TXQ_SIZE * sizeof(struct PbufInfo)); in CreateHiethPrivData()
61 if (!pstPrivData->ram->pbufInfo) { in CreateHiethPrivData()
68 OsalMemFree((void *)pstPrivData->ram->rxNetbuf); in CreateHiethPrivData()
70 OsalMemFree((void *)pstPrivData->ram->txqInfo); in CreateHiethPrivData()
[all …]
|
| /device/soc/hisilicon/hi3861v100/sdk_liteos/build/link/ |
| D | loaderboot_ecc.lds | 6 /* ram for stack */
8 /* ram for common bss and data */
10 /* ram for fix rom bss and data */
12 /* ram for code rom bss and data */
14 /* ram for heap */
16 /* ram for loaderboot */
117 *(.ram.text*)
|
| D | loaderboot_sha256.lds | 6 /* ram for stack */
8 /* ram for common bss and data */
10 /* ram for fix rom bss and data */
12 /* ram for code rom bss and data */
14 /* ram for heap */
16 /* ram for loaderboot */
117 *(.ram.text*)
|
| D | loaderboot_rsa.lds | 6 /* ram for stack */
8 /* ram for common bss and data */
10 /* ram for fix rom bss and data */
12 /* ram for code rom bss and data */
14 /* ram for heap */
16 /* ram for loaderboot */
117 *(.ram.text*)
|
| D | flashboot_ecc.lds | 8 /* ram for stack */
10 /* ram for common bss and data */
12 /* ram for fix rom bss and data */
14 /* ram for code rom bss and data */
18 /* ram for flashboot */
20 /* ram for heap */
|
| D | flashboot_rsa.lds | 8 /* ram for stack */
10 /* ram for common bss and data */
12 /* ram for fix rom bss and data */
14 /* ram for code rom bss and data */
18 /* ram for flashboot */
20 /* ram for heap */
|
| D | flashboot_sha256.lds | 8 /* ram for stack */
10 /* ram for common bss and data */
12 /* ram for fix rom bss and data */
14 /* ram for code rom bss and data */
18 /* ram for flashboot */
20 /* ram for heap */
|
| D | link.ld.S | 265 KEEP(*(.crypto.ram.text))
379 KEEP(*(.kernel.ram.text))
380 KEEP(*(.ram.kernel))
381 KEEP(*(.bsp.ram.text))
385 SORT(*)(.kernel.ram.text)
386 SORT(*)(.ram.kernel)
387 SORT(*)(.bsp.ram.text)
556 KEEP(SORT(*)(.lowpower.ram.bss*))
589 KEEP(SORT(*)(.lowpower.ram.bss*))
|
| /device/qemu/arm_mps3_an547/liteos_m/board/ |
| D | liteos.ld | 45 ram(rwx) : ORIGIN = PS_RAM_START, LENGTH = PS_RAM_SIZE
70 } > ram
75 } > ram
84 } > ram
93 } > ram
97 } > ram
|
| /device/qemu/arm_mps2_an386/liteos_m/board/ |
| D | liteos.ld | 45 ram(rwx) : ORIGIN = PS_RAM_START, LENGTH = PS_RAM_SIZE
70 } > ram
75 } > ram
84 } > ram
93 } > ram
97 } > ram
|
| /device/qemu/riscv32_virt/liteos_m/board/ |
| D | liteos.ld | 46 ram(rwx) : ORIGIN = RAM_ADDR_START, LENGTH = RAM_ADDR_SIZE
67 } > ram AT > flash
95 } > ram AT > flash
180 } > ram
189 } > ram
197 } > ram
202 } > ram
|
| /device/soc/st/stm32f407zg/uniproton/board/ |
| D | rtos.ld | 46 ram(rwx) : ORIGIN = PS_RAM_START, LENGTH = PS_RAM_SIZE
171 } > ram AT > flash
184 } > ram
195 } > ram
199 } > ram
|
| /device/soc/rockchip/common/sdk_linux/drivers/staging/blackbox/ |
| D | Kconfig | 54 tristate "blackbox fault log storage by pstore ram"
60 This option enables saving fault logs with pstore ram by blackbox when a
61 panic occurs. It depends on supporting pstore ram.
84 The default materail is ram directly. It's easy, but not work offen.
|
| /device/soc/winnermicro/wm800/board/src/bt/ |
| D | BUILD.gn | 105 "blehost/nimble/host/store/ram/src/ble_store_ram.c",
134 "blehost/nimble/host/store/ram/include",
135 "blehost/nimble/host/store/ram/include/store/ram",
|
| /device/soc/hisilicon/common/platform/hieth-sf/src/ |
| D | ctrl.c | 299 pbuf = priv->ram->pbufInfo + ld->txqTail; in HiethXmitReleasePkt()
343 pbInfo = &(priv->ram->pbufInfo[ld->txqHead]); in HiethXmitGso()
408 priv->ram->rxNetbuf[priv->rxFeed] = netBuf; in HiethFeedHw()
|
| D | interface.c | 296 netBuf = priv->ram->rxNetbuf[priv->rxRelease]; in HiethDeliver()
457 ld->txq = priv->ram->txqInfo; in HiethHwInit()
|
| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6360/ |
| D | CMakeLists.txt | 55 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/ram.ld PARENT_SCOPE)
|
| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6750/ |
| D | CMakeLists.txt | 58 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/ram.ld PARENT_SCOPE)
|
| /device/soc/hisilicon/common/platform/hieth-sf/include/internal/ |
| D | eth_mac.h | 96 volatile EthRamCfg *ram; member
|
| /device/soc/hpmicro/sdk/hpm_sdk/boards/hpm6750evkmini/ |
| D | README.md | 5 The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also,…
|
| /device/soc/hpmicro/sdk/hpm_sdk/boards/hpm6750evk/ |
| D | README.md | 5 The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also,…
|
| /device/soc/hpmicro/sdk/hpm_sdk/boards/hpm6750evk2/ |
| D | README.md | 5 The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also,…
|
| /device/qemu/x86_64_virt/linux/ |
| D | README_zh.md | 79 主机侧会创建br0的网桥，用于与qemu ram虚拟机设备进行网络通信。
|
| /device/qemu/arm_virt/linux/ |
| D | README_zh.md | 81 主机侧会创建br0的网桥，用于与qemu ram虚拟机设备进行网络通信。
|
| /device/qemu/arm_virt/liteos_a/ |
| D | example.md | 101 "ram": "",
|
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