| /device/soc/hpmicro/sdk/hpm_sdk/drivers/src/ |
| D | hpm_pmp_drv.c | 16 pmp_cfg = read_csr(CSR_PMPCFG0); in read_pmp_cfg()
19 pmp_cfg = read_csr(CSR_PMPCFG1); in read_pmp_cfg()
22 pmp_cfg = read_csr(CSR_PMPCFG2); in read_pmp_cfg()
25 pmp_cfg = read_csr(CSR_PMPCFG3); in read_pmp_cfg()
39 pma_cfg = read_csr(CSR_PMACFG0); in read_pma_cfg()
42 pma_cfg = read_csr(CSR_PMACFG1); in read_pma_cfg()
45 pma_cfg = read_csr(CSR_PMACFG2); in read_pma_cfg()
48 pma_cfg = read_csr(CSR_PMACFG3); in read_pma_cfg()
218 ret_val = read_csr(CSR_PMPADDR0); in read_pmp_addr()
221 ret_val = read_csr(CSR_PMPADDR1); in read_pmp_addr()
[all …]
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/arch/riscv/ |
| D | pmp.c | 130 …write_csr(NDS_PMPCFG0, ((read_csr(NDS_PMPCFG0) & (~(0xFFLL << ((long)(entry%8) << 3)))) | (((long)… in pmp_tor_config()
133 …write_csr(NDS_PMPCFG2, ((read_csr(NDS_PMPCFG2) & (~(0xFFLL << ((long)(entry%8) << 3)))) | (((long)… in pmp_tor_config()
139 …write_csr(NDS_PMPCFG0, ((read_csr(NDS_PMPCFG0) & (~((0xFF) << ((entry%4) << 3)))) | (((long)pmpcfg… in pmp_tor_config()
142 …write_csr(NDS_PMPCFG1, ((read_csr(NDS_PMPCFG1) & (~((0xFF) << ((entry%4) << 3)))) | (((long)pmpcfg… in pmp_tor_config()
145 …write_csr(NDS_PMPCFG2, ((read_csr(NDS_PMPCFG2) & (~((0xFF) << ((entry%4) << 3)))) | (((long)pmpcfg… in pmp_tor_config()
148 …write_csr(NDS_PMPCFG3, ((read_csr(NDS_PMPCFG3) & (~((0xFF) << ((entry%4) << 3)))) | (((long)pmpcfg… in pmp_tor_config()
210 …write_csr(NDS_PMPCFG0, ((read_csr(NDS_PMPCFG0) & (~(0xFFLL << ((long)(entry%8) << 3)))) | (((long)… in pmp_napot_config()
213 …write_csr(NDS_PMPCFG2, ((read_csr(NDS_PMPCFG2) & (~(0xFFLL << ((long)(entry%8) << 3)))) | (((long)… in pmp_napot_config()
219 …write_csr(NDS_PMPCFG0, ((read_csr(NDS_PMPCFG0) & (~((0xFF) << ((entry%4) << 3)))) | (((long)pmpcfg… in pmp_napot_config()
222 …write_csr(NDS_PMPCFG1, ((read_csr(NDS_PMPCFG1) & (~((0xFF) << ((entry%4) << 3)))) | (((long)pmpcfg… in pmp_napot_config()
[all …]
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| D | cache.c | 186 if (read_csr(NDS_MMSC_CFG) & CCTLCSR_MSK) { in show_cache_config_info()
189 if (read_csr(NDS_MMSC_CFG) & VCCTL_MSK) { in show_cache_config_info()
204 icm_cfg = read_csr(NDS_MICM_CFG); in show_cache_config_info()
234 dcm_cfg = read_csr(NDS_MDCM_CFG); in show_cache_config_info()
263 if (read_csr(NDS_MCACHE_CTL) & 0x1) { in show_cache_config_info()
267 if (read_csr(NDS_MCACHE_CTL) & 0x2) { in show_cache_config_info()
271 if (!(read_csr(NDS_MCACHE_CTL) & 0x3)) { in show_cache_config_info()
282 if(read_csr(NDS_MMSC_CFG) & CCTLCSR_MSK) { in flush_dcache()
285 dsize = (unsigned int)(1 << (((read_csr(NDS_MDCM_CFG) & DSIZE_MSK) >> 6) + 2)); in flush_dcache()
288 if ((read_csr(NDS_MMSC_CFG) & VCCTL_MSK)) { in flush_dcache()
[all …]
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| D | trap_base.c | 238 BK_DUMP_OUT("838 mtvec x 0x%lx\r\n", read_csr(NDS_MTVEC)); in arch_dump_cpu_registers()
239 BK_DUMP_OUT("897 mscratch x 0x%lx\r\n", read_csr(NDS_MSCRATCH)); in arch_dump_cpu_registers()
242 BK_DUMP_OUT("900 mtval x 0x%lx\r\n", read_csr(NDS_MTVAL)); in arch_dump_cpu_registers()
243 BK_DUMP_OUT("2058 mdcause x 0x%lx\r\n", read_csr(NDS_MDCAUSE)); in arch_dump_cpu_registers()
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| D | riscv.c | 101 if (read_csr(NDS_MMISC_CTL) & (1 << 1)) { in system_init()
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| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6360/toolchains/ |
| D | trap.c | 109 long mcause = read_csr(CSR_MCAUSE); in irq_handler_trap()
110 long mepc = read_csr(CSR_MEPC); in irq_handler_trap()
111 long mstatus = read_csr(CSR_MSTATUS); in irq_handler_trap()
113 long mxstatus = read_csr(CSR_MXSTATUS); in irq_handler_trap()
116 int ucode = read_csr(CSR_UCODE); in irq_handler_trap()
197 long scause = read_csr(CSR_SCAUSE); in irq_handler_s_trap()
198 long sepc = read_csr(CSR_SEPC); in irq_handler_s_trap()
199 long sstatus = read_csr(CSR_SSTATUS); in irq_handler_s_trap()
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| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6750/toolchains/ |
| D | trap.c | 98 long mcause = read_csr(CSR_MCAUSE); in irq_handler_trap()
99 long mepc = read_csr(CSR_MEPC); in irq_handler_trap()
100 long mstatus = read_csr(CSR_MSTATUS); in irq_handler_trap()
102 long mxstatus = read_csr(CSR_MXSTATUS); in irq_handler_trap()
105 int ucode = read_csr(CSR_UCODE); in irq_handler_trap()
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| /device/soc/telink/b91/b91_ble_sdk/drivers/B91/ |
| D | core.h | 23 #define read_csr(reg) __nds__csrr(reg) macro
33 #define save_csr(r) long __##r = read_csr(r)
63 unsigned int r = read_csr(NDS_MIE); in core_interrupt_disable()
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| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6750/ |
| D | hpm_l1c_drv.h | 222 return read_csr(CSR_MCACHE_CTL); in l1c_get_control()
263 return read_csr(CSR_MCCTLBEGINADDR); in l1c_cctl_get_address()
323 *ecc_data = read_csr(CSR_MECC_CODE); in l1c_cctl_address_cmd_read()
324 return read_csr(CSR_MCCTLDATA); in l1c_cctl_address_cmd_read()
381 return read_csr(CSR_MICM_CFG); in l1c_ic_get_config()
391 return read_csr(CSR_MDCM_CFG); in l1c_dc_get_config()
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| D | hpm_clock_drv.c | 479 uint32_t resultl_first = read_csr(CSR_CYCLE); in get_core_mcycle()
480 uint32_t resulth = read_csr(CSR_CYCLEH); in get_core_mcycle()
481 uint32_t resultl_second = read_csr(CSR_CYCLE); in get_core_mcycle()
485 resulth = read_csr(CSR_CYCLEH); in get_core_mcycle()
509 uint32_t hart_id = read_csr(CSR_MHARTID); in clock_update_core_clock()
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| D | system.c | 36 uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); in system_init()
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| D | hpm_l1c_drv.c | 27 if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { in l1c_op()
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| D | hpm_interrupt.h | 297 #define SAVE_CSR(r) register long __##r = read_csr(r);
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| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6360/ |
| D | hpm_l1c_drv.h | 222 return read_csr(CSR_MCACHE_CTL); in l1c_get_control()
263 return read_csr(CSR_MCCTLBEGINADDR); in l1c_cctl_get_address()
323 *ecc_data = read_csr(CSR_MECC_CODE); in l1c_cctl_address_cmd_read()
324 return read_csr(CSR_MCCTLDATA); in l1c_cctl_address_cmd_read()
381 return read_csr(CSR_MICM_CFG); in l1c_ic_get_config()
391 return read_csr(CSR_MDCM_CFG); in l1c_dc_get_config()
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| D | hpm_clock_drv.c | 529 uint32_t resultl_first = read_csr(CSR_CYCLE); in get_core_mcycle()
530 uint32_t resulth = read_csr(CSR_CYCLEH); in get_core_mcycle()
531 uint32_t resultl_second = read_csr(CSR_CYCLE); in get_core_mcycle()
535 resulth = read_csr(CSR_MCYCLEH); in get_core_mcycle()
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| D | system.c | 30 uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); in system_init()
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| D | hpm_l1c_drv.c | 27 if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { in l1c_op()
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| D | hpm_interrupt.h | 492 #define SAVE_CSR(r) register long __##r = read_csr(r);
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| /device/soc/hpmicro/sdk/hpm_sdk/arch/riscv/ |
| D | riscv_core.h | 55 #define read_csr(csr_num) ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v;… macro
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/components/bk_os/liteos_m_mst/ |
| D | port.c | 119 uxSavedStatusValue = read_csr(NDS_MIE); in port_disable_mie_flag()
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/arch/riscv/include/ |
| D | core_v5.h | 137 #define read_csr(reg) __nds__csrr(reg) macro
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| D | arch_interrupt.h | 85 #define SAVE_CSR(r) long __##r = read_csr(r);
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| /device/soc/hpmicro/sdk/hpm_sdk/components/dma_manager/ |
| D | hpm_dma_manager.c | 107 uint32_t level = read_csr(CSR_MSTATUS); in dma_manager_enter_critical()
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| /device/board/kaihong/khdvk_3566b/wifi/bcmdhd_hdf/bcmdhd/include/ |
| D | wlioctl.h | 20480 uint32 read_csr; /* Read Back CSR */ member
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| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/ |
| D | wlioctl.h | 19870 uint32 read_csr; /* Read Back CSR */ member
|