1 /*
2 * Copyright (c) 2021 iSoftStone Device Co., Ltd.
3 *
4 * HDF is dual licensed: you can use it either under the terms of
5 * the GPL, or the BSD license, at your option.
6 * See the LICENSE file in the root of this repository for complete details.
7 */
8
9 #include "rk3399_dai_ops.h"
10 #include "audio_host.h"
11 #include "audio_control.h"
12 #include "audio_dai_if.h"
13 #include "audio_dai_base.h"
14 #include "audio_platform_base.h"
15 #include "audio_driver_log.h"
16 #include "osal_io.h"
17 #include "osal_time.h"
18 #include "audio_stream_dispatch.h"
19
20 #include <linux/device.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/of.h>
24 #include <linux/regmap.h>
25 #include <linux/of_device.h>
26 #include <linux/ioport.h>
27 #include <linux/clk.h>
28 #include <linux/clk/rockchip.h>
29 #include <sound/dmaengine_pcm.h>
30 #include <linux/pm_runtime.h>
31
32
33 #define HDF_LOG_TAG rk3399_dai_ops
34 #define HALF_MILLION (500000)
35 #define ONE_MILLION (1000000)
36 #define NUM_TWO (2)
37 #define NUM_SIXTEEN (16)
38 #define NUM_TWENTY_FOUR (24)
39
40 void *g_regDaiBase = NULL;
41
42 struct regmap *regmap = NULL;
43 /* I2S REGS */
44 #define I2S_TXCR (0x0000)
45 #define I2S_RXCR (0x0004)
46 #define I2S_CKR (0x0008)
47 #define I2S_FIFOLR (0x000c)
48 #define I2S_DMACR (0x0010)
49 #define I2S_INTCR (0x0014)
50 #define I2S_INTSR (0x0018)
51 #define I2S_XFER (0x001c)
52 #define I2S_CLR (0x0020)
53 #define I2S_TXDR (0x0024)
54 #define I2S_RXDR (0x0028)
55
56 /*
57 * DMACR
58 * DMA control register
59 */
60 #define I2S_DMACR_RDE_SHIFT 24
61 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
62 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
63 #define I2S_DMACR_RDL_SHIFT 16
64 #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
65 #define I2S_DMACR_TDE_SHIFT 8
66 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
67 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
68 #define I2S_DMACR_TDL_SHIFT 0
69 #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
70
71 /*
72 * XFER
73 * Transfer start register
74 */
75 #define I2S_XFER_RXS_SHIFT 1
76 #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
77 #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
78 #define I2S_XFER_TXS_SHIFT 0
79 #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
80 #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
81
82 /*
83 * CLR
84 * clear SCLK domain logic register
85 */
86 #define I2S_CLR_RXC BIT(1)
87 #define I2S_CLR_TXC BIT(0)
88
89 #define I2S_CKR_MDIV_SHIFT 16
90 #define I2S_CKR_TSD_SHIFT 0
91 #define I2S_CKR_RSD_SHIFT 8
92
93 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
94
95 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
96 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
97
98 #define I2S_CKR_TRCM_SHIFT 28
99 #define I2S_CKR_TRCM(x) ((x) << I2S_CKR_TRCM_SHIFT)
100 #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT)
101 #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT)
102 #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT)
103 #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT)
104 #define I2S_CKR_MSS_SHIFT 27
105 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
106 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
107 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
108 #define I2S_CKR_CKP_SHIFT 26
109 #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_CKP_SHIFT)
110 #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_CKP_SHIFT)
111 #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT)
112 #define I2S_CKR_RLP_SHIFT 25
113 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
114 #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_RLP_SHIFT)
115 #define I2S_CKR_RLP_MASK (1 << I2S_CKR_RLP_SHIFT)
116 #define I2S_CKR_TLP_SHIFT 24
117 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
118 #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT)
119 #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT)
120 #define I2S_CKR_MDIV_SHIFT 16
121 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
122 #define I2S_CKR_RSD_SHIFT 8
123 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
124 #define I2S_CKR_TSD_SHIFT 0
125 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
126
127 /* io direction cfg register */
128 #define I2S_IO_DIRECTION_MASK (7)
129 #define I2S_IO_8CH_OUT_2CH_IN (0)
130 #define I2S_IO_6CH_OUT_4CH_IN (4)
131 #define I2S_IO_4CH_OUT_6CH_IN (6)
132 #define I2S_IO_2CH_OUT_8CH_IN (7)
133 /* channel select */
134 #define I2S_CSR_SHIFT 15
135 #define I2S_CHN_2 (0 << I2S_CSR_SHIFT)
136 #define I2S_CHN_4 (1 << I2S_CSR_SHIFT)
137 #define I2S_CHN_6 (2 << I2S_CSR_SHIFT)
138 #define I2S_CHN_8 (3 << I2S_CSR_SHIFT)
139 /*
140 * TXDR
141 * Transimt FIFO data register, write only.
142 */
143 #define I2S_TXDR_MASK (0xff)
144
145 /*
146 * RXDR
147 * Receive FIFO data register, write only.
148 */
149 #define I2S_RXDR_MASK (0xff)
150 /*
151 * TXCR
152 * transmit operation control register
153 */
154 #define I2S_TXCR_RCNT_SHIFT 17
155 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
156 #define I2S_TXCR_CSR_SHIFT 15
157 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
158 #define I2S_TXCR_HWT BIT(14)
159 #define I2S_TXCR_SJM_SHIFT 12
160 #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
161 #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
162 #define I2S_TXCR_FBM_SHIFT 11
163 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
164 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
165 #define I2S_TXCR_IBM_SHIFT 9
166 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
167 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
168 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
169 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
170 #define I2S_TXCR_PBM_SHIFT 7
171 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
172 #define I2S_TXCR_TFS_SHIFT 5
173 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
174 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
175 #define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
176 #define I2S_TXCR_VDW_SHIFT 0
177 #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
178
179
180 #define I2S_RXCR_CSR_SHIFT 15
181 #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT)
182 #define I2S_RXCR_HWT BIT(14)
183 #define I2S_RXCR_SJM_SHIFT 12
184 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
185 #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
186 #define I2S_RXCR_FBM_SHIFT 11
187 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
188 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
189 #define I2S_RXCR_IBM_SHIFT 9
190 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
191 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
192 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
193 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
194 #define I2S_RXCR_PBM_SHIFT 7
195 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
196 #define I2S_RXCR_TFS_SHIFT 5
197 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
198 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
199 #define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
200 #define I2S_RXCR_VDW_SHIFT 0
201 #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
202
I2sRxcrPbmMode(uint32_t x)203 inline uint32_t I2sRxcrPbmMode(uint32_t x) {
204 return ((x) << I2S_RXCR_PBM_SHIFT);
205 }
206
I2sDmacrRdl(uint32_t x)207 inline uint32_t I2sDmacrRdl(uint32_t x) {
208 return (((x) - 1) << I2S_DMACR_RDL_SHIFT);
209 }
210
I2sDmacrTdl(uint32_t x)211 inline uint32_t I2sDmacrTdl(uint32_t x) {
212 return ((x) << I2S_DMACR_TDL_SHIFT);
213 }
214
I2sCkrMdiv(uint32_t x)215 inline uint32_t I2sCkrMdiv(uint32_t x) {
216 return (((x) - 1) << I2S_CKR_MDIV_SHIFT);
217 }
218
I2sCkrTsd(uint32_t x)219 inline uint32_t I2sCkrTsd(uint32_t x) {
220 return (((x) - 1) << I2S_CKR_TSD_SHIFT);
221 }
222
I2sCkrRsd(uint32_t x)223 inline uint32_t I2sCkrRsd(uint32_t x) {
224 return (((x) - 1) << I2S_CKR_RSD_SHIFT);
225 }
226
I2sRxcrCsr(uint32_t x)227 inline uint32_t I2sRxcrCsr(uint32_t x) {
228 return ((x) << I2S_RXCR_CSR_SHIFT);
229 }
230
I2sTxcrCsr(uint32_t x)231 inline uint32_t I2sTxcrCsr(uint32_t x) {
232 return ((x) << I2S_TXCR_CSR_SHIFT);
233 }
234
I2sTxcrPbmMode(uint32_t x)235 inline uint32_t I2sTxcrPbmMode(uint32_t x) {
236 return ((x) << I2S_TXCR_PBM_SHIFT);
237 }
238
I2sTxcrVdw(uint32_t x)239 inline uint32_t I2sTxcrVdw(uint32_t x) {
240 return (((x) - 1) << I2S_TXCR_VDW_SHIFT);
241 }
242
I2sRxcrVdw(uint32_t x)243 inline uint32_t I2sRxcrVdw(uint32_t x) {
244 return (((x) - 1) << I2S_RXCR_VDW_SHIFT);
245 }
246
247 struct rk_i2s_pins {
248 u32 reg_offset;
249 u32 shift;
250 };
251
252 struct rk_i2s_dev {
253 struct device *dev;
254
255 struct clk *hclk;
256 struct clk *mclk;
257 struct clk *mclk_root;
258
259 struct snd_dmaengine_dai_dma_data capture_dma_data;
260 struct snd_dmaengine_dai_dma_data playback_dma_data;
261
262 struct regmap *regmap;
263 struct regmap *grf;
264 struct reset_control *reset_m;
265 struct reset_control *reset_h;
266
267 /*
268 * Used to indicate the tx/rx status.
269 * I2S controller hopes to start the tx and rx together,
270 * also to stop them when they are both try to stop.
271 */
272 bool tx_start;
273 bool rx_start;
274 bool is_master_mode;
275 const struct rk_i2s_pins *pins;
276 unsigned int bclk_fs;
277 unsigned int clk_trcm;
278
279 unsigned int mclk_root_rate;
280 unsigned int mclk_root_initial_rate;
281 int clk_ppm;
282 bool mclk_calibrate;
283 };
284
285 struct rk_i2s_dev *g_rkI2SDev = NULL;
286
287 struct rk_i2s_dev *GetRockChipI2SDevice(void);
288
DaiDeviceReadReg(unsigned long virtualAddress,uint32_t reg,uint32_t * val)289 int32_t DaiDeviceReadReg(unsigned long virtualAddress, uint32_t reg, uint32_t *val)
290 {
291 if (val == NULL) {
292 AUDIO_DRIVER_LOG_ERR("param val is null.");
293 return HDF_FAILURE;
294 }
295
296 AUDIO_DRIVER_LOG_DEBUG("reg virtualAddress = 0x%x val = 0x%x ", virtualAddress, reg);
297
298 if (reg == 0xffffff) {
299 AUDIO_DRIVER_LOG_DEBUG("reg val is invalue.");
300 return HDF_SUCCESS;
301 }
302 *val = 0;
303
304 AUDIO_DRIVER_LOG_DEBUG("RockChipRead reg = 0x%x val = 0x%x.", reg, *val);
305
306 return HDF_SUCCESS;
307 }
308
DaiDeviceWriteReg(unsigned long virtualAddress,uint32_t reg,uint32_t value)309 int32_t DaiDeviceWriteReg(unsigned long virtualAddress, uint32_t reg, uint32_t value)
310 {
311 if (reg == 0xffffff) {
312 AUDIO_DRIVER_LOG_DEBUG("reg val is invalue.");
313 return HDF_SUCCESS;
314 }
315
316 AUDIO_DRIVER_LOG_DEBUG("reg virtualAddress = 0x%x val = 0x%x val = %d", virtualAddress, reg, value);
317
318 return HDF_SUCCESS;
319 }
320
DaiDeviceRegUpdateBits(unsigned int reg,unsigned int mask,unsigned int val)321 int32_t DaiDeviceRegUpdateBits(unsigned int reg, unsigned int mask, unsigned int val)
322 {
323 AUDIO_DRIVER_LOG_DEBUG("reg reg = 0x%x mask = 0x%x val = %d", reg, mask, val);
324 return HDF_SUCCESS;
325 }
326
DaiDeviceInit(struct AudioCard * audioCard,const struct DaiDevice * dai)327 int32_t DaiDeviceInit(struct AudioCard *audioCard, const struct DaiDevice *dai)
328 {
329 int regAddr;
330 int ret;
331
332 AUDIO_DRIVER_LOG_DEBUG("entry.");
333
334 if (dai == NULL || dai->devData == NULL) {
335 AUDIO_DRIVER_LOG_ERR("dai is nullptr.");
336 return HDF_FAILURE;
337 }
338 struct DaiData *data = dai->devData;
339 struct AudioRegCfgData *regConfig = dai->devData->regConfig;
340 if (regConfig == NULL) {
341 AUDIO_DRIVER_LOG_ERR("regConfig is nullptr.");
342 return HDF_FAILURE;
343 }
344
345 data->regVirtualAddr = regAddr;
346
347 if (DaiSetConfigInfo(data) != HDF_SUCCESS) {
348 AUDIO_DRIVER_LOG_ERR("set config info fail.");
349 return HDF_FAILURE;
350 }
351
352 ret = AudioAddControls(audioCard, data->controls, data->numControls);
353 if (ret != HDF_SUCCESS) {
354 AUDIO_DRIVER_LOG_ERR("add controls failed.");
355 return HDF_FAILURE;
356 }
357
358 if (data->daiInitFlag == true) {
359 AUDIO_DRIVER_LOG_DEBUG("dai init complete!");
360 return HDF_SUCCESS;
361 }
362
363 data->daiInitFlag = true;
364
365 AUDIO_DRIVER_LOG_DEBUG("success.");
366
367 return HDF_SUCCESS;
368 }
369
DaiTrigger(const struct AudioCard * card,int cmd,const struct DaiDevice * device)370 int32_t DaiTrigger(const struct AudioCard *card, int cmd, const struct DaiDevice *device)
371 {
372 AUDIO_DRIVER_LOG_DEBUG("entry.");
373 bool isStart = false;
374
375 (void)card;
376 (void)device;
377
378 switch (cmd) {
379 case AUDIO_DRV_PCM_IOCTL_RENDER_START:
380 case AUDIO_DRV_PCM_IOCTL_RENDER_RESUME:
381 AUDIO_DRIVER_LOG_DEBUG("---------RENDER_START--------------.");
382 regmap_update_bits(g_rkI2SDev->regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
383 isStart = true;
384 break;
385 case AUDIO_DRV_PCM_IOCTL_RENDER_STOP:
386 case AUDIO_DRV_PCM_IOCTL_RENDER_PAUSE:
387 AUDIO_DRIVER_LOG_DEBUG("---------RENDER_PAUSE_OR_STOP--------------.");
388 regmap_update_bits(g_rkI2SDev->regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
389 break;
390
391 case AUDIO_DRV_PCM_IOCTL_CAPTURE_START:
392 case AUDIO_DRV_PCM_IOCTL_CAPTURE_RESUME:
393 AUDIO_DRIVER_LOG_DEBUG("---------CAPTURE_START--------------.");
394 regmap_update_bits(g_rkI2SDev->regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
395 isStart = true;
396 break;
397 case AUDIO_DRV_PCM_IOCTL_CAPTURE_STOP:
398 case AUDIO_DRV_PCM_IOCTL_CAPTURE_PAUSE:
399 AUDIO_DRIVER_LOG_DEBUG("---------CAPTURE_PAUSE_OR_STOP--------------.");
400 g_rkI2SDev->rx_start = false;
401 regmap_update_bits(g_rkI2SDev->regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
402 break;
403
404 default:
405 AUDIO_DRIVER_LOG_ERR("invalude cmd id: %d.", cmd);
406 return HDF_FAILURE;
407 }
408
409 if (isStart) {
410 AUDIO_DRIVER_LOG_DEBUG("---------isStart--------------.");
411 regmap_update_bits(g_rkI2SDev->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START,
412 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
413 } else { // if (!g_rkI2SDev->rx_start) {
414 AUDIO_DRIVER_LOG_DEBUG("---------g_rkI2SDev->rx_start=false--------------.");
415 regmap_update_bits(g_rkI2SDev->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START,
416 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
417
418 udelay(0d150);
419 regmap_update_bits(g_rkI2SDev->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC,
420 I2S_CLR_TXC | I2S_CLR_RXC);
421 }
422
423 AUDIO_DRIVER_LOG_DEBUG("success.");
424 return HDF_SUCCESS;
425 }
426
rockchip_i2s_clk_set_rate(struct rk_i2s_dev * i2s,struct clk * clk,unsigned long rate,int ppm)427 static int rockchip_i2s_clk_set_rate(struct rk_i2s_dev *i2s,
428 struct clk *clk, unsigned long rate,
429 int ppm)
430 {
431 unsigned long rate_target;
432 int delta, ret;
433
434 if (ppm == i2s->clk_ppm) {
435 return 0;
436 }
437
438 ret = rockchip_pll_clk_compensation(clk, ppm);
439 if (ret != -ENOSYS)
440 goto out;
441
442 delta = (ppm < 0) ? -1 : 1;
443 delta *= (int)div64_u64((uint64_t)rate * (uint64_t)abs(ppm) + HALF_MILLION, ONE_MILLION);
444
445 rate_target = rate + delta;
446
447 if (!rate_target) {
448 return HDF_FAILURE;
449 }
450
451 ret = clk_set_rate(clk, rate_target);
452 if (ret) {
453 return ret;
454 }
455
456 out:
457 if (!ret)
458 i2s->clk_ppm = ppm;
459
460 return ret;
461 }
462
rockchip_i2s_set_fmt(void)463 static int rockchip_i2s_set_fmt(void)
464 {
465 unsigned int mask = 0, val = 0;
466 int ret = 0;
467 AUDIO_DRIVER_LOG_DEBUG("%s -------------entry ----------- \n", __func__);
468 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
469 pm_runtime_get_sync(g_rkI2SDev->dev);
470
471 mask = I2S_CKR_MSS_MASK;
472 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
473 case SND_SOC_DAIFMT_CBS_CFS:
474 /* Set source clock in Master mode */
475 val = I2S_CKR_MSS_MASTER;
476 g_rkI2SDev->is_master_mode = true;
477 break;
478 case SND_SOC_DAIFMT_CBM_CFM:
479 val = I2S_CKR_MSS_SLAVE;
480 g_rkI2SDev->is_master_mode = false;
481 break;
482 default:
483 AUDIO_DRIVER_LOG_ERR("------------default ----------- ");
484 ret = HDF_FAILURE;
485 }
486
487 regmap_update_bits(g_rkI2SDev->regmap, I2S_CKR, mask, val);
488
489 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
490 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
491 case SND_SOC_DAIFMT_NB_NF:
492 val = I2S_CKR_CKP_NORMAL |
493 I2S_CKR_TLP_NORMAL |
494 I2S_CKR_RLP_NORMAL;
495 break;
496 case SND_SOC_DAIFMT_NB_IF:
497 val = I2S_CKR_CKP_NORMAL |
498 I2S_CKR_TLP_INVERTED |
499 I2S_CKR_RLP_INVERTED;
500 break;
501 case SND_SOC_DAIFMT_IB_NF:
502 val = I2S_CKR_CKP_INVERTED |
503 I2S_CKR_TLP_NORMAL |
504 I2S_CKR_RLP_NORMAL;
505 break;
506 case SND_SOC_DAIFMT_IB_IF:
507 val = I2S_CKR_CKP_INVERTED |
508 I2S_CKR_TLP_INVERTED |
509 I2S_CKR_RLP_INVERTED;
510 break;
511 default:
512 AUDIO_DRIVER_LOG_ERR("------------default ----------- ");
513 ret = HDF_FAILURE;
514 }
515
516 regmap_update_bits(g_rkI2SDev->regmap, I2S_CKR, mask, val);
517
518 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
519 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
520 case SND_SOC_DAIFMT_RIGHT_J:
521 val = I2S_TXCR_IBM_RSJM;
522 break;
523 case SND_SOC_DAIFMT_LEFT_J:
524 val = I2S_TXCR_IBM_LSJM;
525 break;
526 case SND_SOC_DAIFMT_I2S:
527 val = I2S_TXCR_IBM_NORMAL;
528 break;
529 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
530 val = I2S_TXCR_TFS_PCM | I2sTxcrPbmMode(1);
531 break;
532 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
533 val = I2S_TXCR_TFS_PCM;
534 break;
535 default:
536 AUDIO_DRIVER_LOG_ERR("------------default ----------- ");
537 ret = HDF_FAILURE;
538 }
539
540 regmap_update_bits(g_rkI2SDev->regmap, I2S_TXCR, mask, val);
541
542 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
543 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
544 case SND_SOC_DAIFMT_RIGHT_J:
545 val = I2S_RXCR_IBM_RSJM;
546 break;
547 case SND_SOC_DAIFMT_LEFT_J:
548 val = I2S_RXCR_IBM_LSJM;
549 break;
550 case SND_SOC_DAIFMT_I2S:
551 val = I2S_RXCR_IBM_NORMAL;
552 break;
553 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
554 val = I2S_RXCR_TFS_PCM | I2sRxcrPbmMode(1);
555 break;
556 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
557 val = I2S_RXCR_TFS_PCM;
558 break;
559 default:
560 AUDIO_DRIVER_LOG_ERR("------------default ----------- ");
561 ret = HDF_FAILURE;
562 }
563
564 regmap_update_bits(g_rkI2SDev->regmap, I2S_RXCR, mask, val);
565 AUDIO_DRIVER_LOG_ERR("------------success ----------- ");
566 ret = HDF_SUCCESS;
567 return ret;
568 }
569
DaiStartup(const struct AudioCard * card,const struct DaiDevice * device)570 int32_t DaiStartup(const struct AudioCard *card, const struct DaiDevice *device)
571 {
572 unsigned int root_rate, div, delta;
573 uint64_t ppm;
574 unsigned int rate = 0xac4400;
575 AUDIO_DRIVER_LOG_DEBUG("entry.");
576 int ret;
577 g_rkI2SDev = GetRockChipI2SDevice();
578
579 if (g_rkI2SDev == NULL) {
580 AUDIO_DRIVER_LOG_ERR("g_rkI2SDev is nullptr.");
581 return HDF_FAILURE;
582 }
583
584 rockchip_i2s_set_fmt();
585
586 if (g_rkI2SDev->mclk_calibrate) {
587 AUDIO_DRIVER_LOG_DEBUG("------------mclk_calibrate entry----------.");
588 ret = rockchip_i2s_clk_set_rate(g_rkI2SDev, g_rkI2SDev->mclk_root,
589 g_rkI2SDev->mclk_root_rate, 0);
590 if (ret) {
591 AUDIO_DRIVER_LOG_DEBUG("------------mclk_calibrate ret=%d----------.", ret);
592 return ret;
593 }
594
595 root_rate = g_rkI2SDev->mclk_root_rate;
596 delta = abs(root_rate % rate - rate);
597 AUDIO_DRIVER_LOG_DEBUG("------------mclk_calibrate root_rate=%d----delta=%d------.", root_rate, delta);
598 ppm = div64_u64((uint64_t)delta * ONE_MILLION, (uint64_t)root_rate);
599 if (ppm) {
600 div = DIV_ROUND_CLOSEST(g_rkI2SDev->mclk_root_initial_rate, rate);
601 if (!div) {
602 AUDIO_DRIVER_LOG_DEBUG("------------mclk_calibrate rate=%d----------.", rate);
603 }
604 root_rate = rate * round_up(div, NUM_TWO);
605 ret = clk_set_rate(g_rkI2SDev->mclk_root, root_rate);
606 if (ret) {
607 AUDIO_DRIVER_LOG_DEBUG("------------mclk_calibrate ret1=%d----------.", ret);
608 return ret;
609 }
610 g_rkI2SDev->mclk_root_rate = clk_get_rate(g_rkI2SDev->mclk_root);
611 }
612 }
613
614 ret = clk_set_rate(g_rkI2SDev->mclk, rate);
615 if (ret) {
616 AUDIO_DRIVER_LOG_ERR("Fail to set mclk %d", ret);
617 }
618
619 ret = clk_prepare_enable(g_rkI2SDev->mclk);
620 if (ret) {
621 AUDIO_DRIVER_LOG_ERR("mclock enable failed %d\n", ret);
622 return ret;
623 }
624 ret = clk_prepare_enable(g_rkI2SDev->hclk);
625 if (ret) {
626 AUDIO_DRIVER_LOG_ERR("hclock enable failed %d\n", ret);
627 return ret;
628 }
629
630 ret = clk_enable(g_rkI2SDev->hclk);
631 if (ret) {
632 AUDIO_DRIVER_LOG_DEBUG("Could not register PCM\n");
633 return ret;
634 }
635
636 pm_runtime_enable(g_rkI2SDev->dev);
637
638 AUDIO_DRIVER_LOG_DEBUG("success.");
639 return HDF_SUCCESS;
640 }
641
DaiHwParams(const struct AudioCard * card,const struct AudioPcmHwParams * param)642 int32_t DaiHwParams(const struct AudioCard *card, const struct AudioPcmHwParams *param)
643 {
644 uint32_t bitWidth;
645 unsigned int val = 0;
646 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
647
648 AUDIO_DRIVER_LOG_DEBUG("entry.");
649
650 if (card == NULL || card->rtd == NULL || card->rtd->cpuDai == NULL ||
651 param == NULL || param->cardServiceName == NULL) {
652 AUDIO_DRIVER_LOG_ERR("input para is nullptr.");
653 return HDF_FAILURE;
654 }
655
656 if (DaiCheckSampleRate(param->rate) != HDF_SUCCESS) {
657 return HDF_ERR_NOT_SUPPORT;
658 }
659
660 struct DaiData *data = DaiDataFromCard(card);
661 if (data == NULL) {
662 AUDIO_DRIVER_LOG_ERR("platformHost is nullptr.");
663 return HDF_FAILURE;
664 }
665
666 data->pcmInfo.channels = param->channels;
667
668 if (AudioFramatToBitWidth(param->format, &bitWidth) != HDF_SUCCESS) {
669 return HDF_FAILURE;
670 }
671
672 data->pcmInfo.bitWidth = bitWidth;
673 data->pcmInfo.rate = param->rate;
674 data->pcmInfo.streamType = param->streamType;
675 if (g_rkI2SDev->is_master_mode) {
676
677 mclk_rate = clk_get_rate(g_rkI2SDev->mclk);
678 bclk_rate = g_rkI2SDev->bclk_fs * data->pcmInfo.rate;
679 if (!bclk_rate) {
680 AUDIO_DRIVER_LOG_ERR("bclk_rate is error.");
681 return HDF_FAILURE;
682 }
683 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
684 div_lrck = bclk_rate / data->pcmInfo.rate;
685 regmap_update_bits(g_rkI2SDev->regmap, I2S_CKR,
686 I2S_CKR_MDIV_MASK,
687 I2sCkrMdiv(div_bclk));
688
689 regmap_update_bits(g_rkI2SDev->regmap, I2S_CKR,
690 I2S_CKR_TSD_MASK |
691 I2S_CKR_RSD_MASK,
692 I2sCkrTsd(div_lrck) |
693 I2sCkrRsd(div_lrck));
694 }
695
696 switch (data->pcmInfo.bitWidth) {
697 case DATA_BIT_WIDTH16:
698 val |= I2sTxcrVdw(NUM_SIXTEEN);
699 break;
700
701 case DATA_BIT_WIDTH24:
702 val |= I2sTxcrVdw(NUM_TWENTY_FOUR);
703 break;
704
705 default:
706 return HDF_FAILURE;
707 }
708
709 val |= I2S_CHN_2;
710
711 if (data->pcmInfo.streamType == AUDIO_CAPTURE_STREAM)
712 regmap_update_bits(g_rkI2SDev->regmap, I2S_RXCR,
713 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
714 val);
715 else
716 regmap_update_bits(g_rkI2SDev->regmap, I2S_TXCR,
717 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
718 val);
719
720 if (!IS_ERR(g_rkI2SDev->grf) && g_rkI2SDev->pins) {
721 regmap_read(g_rkI2SDev->regmap, I2S_TXCR, &val);
722 val &= I2S_TXCR_CSR_MASK;
723
724 switch (val) {
725 case I2S_CHN_4:
726 val = I2S_IO_4CH_OUT_6CH_IN;
727 break;
728 case I2S_CHN_6:
729 val = I2S_IO_6CH_OUT_4CH_IN;
730 break;
731 case I2S_CHN_8:
732 val = I2S_IO_8CH_OUT_2CH_IN;
733 break;
734 default:
735 val = I2S_IO_2CH_OUT_8CH_IN;
736 break;
737 }
738
739 val <<= g_rkI2SDev->pins->shift;
740 val |= (I2S_IO_DIRECTION_MASK << g_rkI2SDev->pins->shift) << NUM_SIXTEEN;
741 regmap_write(g_rkI2SDev->grf, g_rkI2SDev->pins->reg_offset, val);
742 }
743
744 regmap_update_bits(g_rkI2SDev->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
745 I2sDmacrTdl(NUM_SIXTEEN));
746 regmap_update_bits(g_rkI2SDev->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
747 I2sDmacrRdl(NUM_SIXTEEN));
748
749 AUDIO_DRIVER_LOG_DEBUG("success.");
750 return HDF_SUCCESS;
751 }
752