Searched refs:set_csr (Results 1 – 14 of 14) sorted by relevance
| /device/soc/telink/b91/b91_ble_sdk/drivers/B91/ |
| D | core.h | 26 #define set_csr(reg, bit) __nds__csrrs(bit, reg) macro
42 save_csr(NDS_MEPC); save_csr(NDS_MSTATUS); save_mxstatus(); set_csr(NDS_MSTATUS, 1 << 3)
76 set_csr(NDS_MIE, en); in core_restore_interrupt()
86 set_csr(NDS_MSTATUS, 1 << 3); in core_interrupt_enable()
87 set_csr(NDS_MIE, (1 << 11) | (1 << 7) | (1 << 3)); in core_interrupt_enable()
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| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6360/ |
| D | hpm_interrupt.h | 36 set_csr(CSR_MSTATUS, mask); in enable_global_irq()
55 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
72 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
91 set_csr(CSR_MIDELEG, mask); in delegate_irq()
114 set_csr(CSR_SSTATUS, mask); in enable_s_global_irq()
142 set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); in enable_s_irq_from_intc()
150 set_csr(CSR_SIE, CSR_SIE_STIE_MASK); in enable_s_mchtmr_irq()
186 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
282 set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); in intc_s_enable_swi()
302 set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); in intc_s_trigger_swi()
[all …]
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| D | hpm_l1c_drv.c | 45 set_csr(CSR_MCACHE_CTL, in l1c_dc_enable()
64 set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK in l1c_ic_enable()
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| /device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6750/ |
| D | hpm_interrupt.h | 36 set_csr(CSR_MSTATUS, mask); in enable_global_irq()
55 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
72 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
107 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
630 set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK);
649 set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \
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| D | hpm_l1c_drv.c | 45 set_csr(CSR_MCACHE_CTL, in l1c_dc_enable()
64 set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK in l1c_ic_enable()
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/arch/riscv/include/ |
| D | arch_interrupt.h | 42 #define HAL_MTIME_ENABLE() set_csr(NDS_MIE, MIP_MTIP)
55 #define HAL_MSWI_ENABLE() set_csr(NDS_MIE, MIP_MSIP)
65 #define HAL_MEIP_ENABLE() set_csr(NDS_MIE, MIP_MEIP)
119 set_csr(NDS_MSTATUS, MSTATUS_MIE);
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| D | riscv_hal.h | 30 #define HalIrqEnable(irq_no) set_csr(NDS_MIE, (1<<irq_no))
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| D | core_v5.h | 140 #define set_csr(reg, bit) __nds__csrrs(bit, reg) macro
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/arch/riscv/ |
| D | arch_interrupt.c | 35 set_csr(NDS_MIE, MIP_MEIP); \
88 set_csr(NDS_MSTATUS, MSTATUS_MIE); in mext_interrupt()
128 set_csr(NDS_MIE, MIP_MTIP); in mext_interrupt()
240 set_csr(NDS_MSTATUS, MSTATUS_MIE); in mtime_handler()
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| D | riscv.c | 110 set_csr(NDS_MMISC_CTL, (1 << 8) | (1 << 6)); in system_init()
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| /device/soc/hpmicro/sdk/hpm_sdk/arch/riscv/ |
| D | riscv_core.h | 38 #define set_csr(csr_num, bit) __asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit)) macro
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| /device/board/beken/bk7235x/liteos_m/adapter/ |
| D | sdk_adapter.c | 25 set_csr(NDS_MIE, (1<<irq_no)); in HalIrqEnable()
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/components/bk_os/liteos_m_mst/ |
| D | port.c | 130 set_csr(NDS_MIE, val); in port_enable_mie_flag()
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/soc/bk7235/hal/ |
| D | sys_hal.c | 471 set_csr(NDS_MIE, MIP_MTIP); in sys_hal_enter_low_voltage()
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