| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/soc/bk7235/soc/ |
| D | sys_struct.h | 34 volatile uint32_t deviceid :32; //0x0[31:0], ,0x53434647,RO
36 uint32_t v;
44 volatile uint32_t versionid :32; //0x1[31:0], ,0x72560001,RO
46 uint32_t v;
54 volatile uint32_t core0_halted : 1; //0x2[0],core0 halt indicate,0,RO
55 volatile uint32_t core1_halted : 1; //0x2[1],core1 halt indicate,0,RO
56 volatile uint32_t reserved2 : 2; //0x2[3:2],Reserved,0,R
57 … volatile uint32_t cpu0_sw_reset : 1; //0x2[4],cpu0_sw_reset indicate,0,RO
58 … volatile uint32_t cpu1_sw_reset : 1; //0x2[5],cpu1_sw_reset indicate,0,RO
59 volatile uint32_t reserved1 : 2; //0x2[7:6],Reserved,0,R
[all …]
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| D | dma2d_struct.h | 29 … volatile uint32_t tran_start : 1; //0x0[ 0],dma2d transfer start.,0,RW
30 … volatile uint32_t tran_suspend : 1; //0x0[ 1],dma2d transfer start.,0,RW
31 … volatile uint32_t tran_abort : 1; //0x0[ 2],dma2d transfer start.,0,RW
32 volatile uint32_t reserved0 : 3; //0x0[ 5: 3],NC,0,RW
33 …volatile uint32_t line_offset_mode : 1; //0x0[ 6],line's offset mode sel: 0:…
34 volatile uint32_t reserved1 : 1; //0x0[ 7],NC,0,RW
35 …volatile uint32_t error_int_en : 1; //0x0[ 8],trabsfer error int ena.,0,…
36 …volatile uint32_t complete_int_en : 1; //0x0[ 9],transfer complete int ena.…
37 …volatile uint32_t waterm_int_en : 1; //0x0[ 10],transfer watermark int ena.…
38 …volatile uint32_t clut_error_int_en : 1; //0x0[ 11],clut transfer error int ena…
[all …]
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| D | system_struct.h | 26 uint32_t v; // 0x0[31:0] Only read default: 0x53434647
31 uint32_t v; // 0x1[31:0] Only read default:0x72560001
38 uint32_t core0_halted: 1; // 0x2[0] core0 halt indicate Only read
39 uint32_t core1_halted: 1; // 0x2[1] core1 halt indicate Only read
40 uint32_t reserved0: 2; // < bit[2:3]
41 uint32_t cpu0_sw_reset: 1; // 0x2[4] cpu0_sw_reset indicate Only read
42 uint32_t cpu1_sw_reset: 1; // 0x2[5] cpu1_sw_reset indicate Only read
43 uint32_t reserved1: 2; // < bit[6:7]
44 uint32_t cpu0_pwr_dw_state: 1; // 0x2[8] cpu0_pwr_dw_state Only read
45 uint32_t cpu1_pwr_dw_state: 1; // 0x2[9] cpu1_pwr_dw_state Only read
[all …]
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| D | icu_struct.h | 25 uint32_t uart1: 1; /**< bit[0], UART1 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
26 uint32_t uart2: 1; /**< bit[1], UART2 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
27 uint32_t i2c1: 1; /**< bit[2], I2C1 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
28 uint32_t irda: 1; /**< bit[3], IRDA clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
29 uint32_t i2c2: 1; /**< bit[4], I2C2 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
30 uint32_t saradc: 1; /**< bit[5], SARADC clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
31 uint32_t spi: 1; /**< bit[6], SPI clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
32 uint32_t pwms: 1; /**< bit[7], PWMS clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
33 uint32_t sdio: 1; /**< bit[8], SDIO clock select, 1-CLK_26M, 0-DCO Divided clk_mux */
34 uint32_t efuse: 1; /**< bit[9], SARADC clock select Audio PLL, if saradc is 0 */
[all …]
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| D | gpio_struct.h | 29 uint32_t gpio_input: 1; /**< bit[0] gpio_input_bit, R */
30 uint32_t gpio_output: 1; /**< bit[1] gpio_output_bit, R/W */
31 uint32_t gpio_input_en: 1; /**< bit[2] gpio_input_en_bit, R/W */
32 uint32_t gpio_output_en: 1; /**< bit[3] gpio_output_en_bit, R/W */
33 uint32_t gpio_pull_mode: 1; /**< bit[4] gpio_pull_mode_bit: 1:pull_up 0:pull_down*/
34 uint32_t gpio_pull_mode_en: 1; /**< bit[5] gpio_pull_mode_en_bit, defult:1R/W */
35 uint32_t gpio_2_func_en: 1; /**< bit[6] gpio_2_func_en_bit, R/W */
36 uint32_t gpio_input_monitor: 1; /**< bit[7] view gpio input values, R/W */
37 uint32_t gpio_capacity: 2; /**< bit[8:9] gpio driver capacity,R/W */
39 uint32_t reserved: 22;
[all …]
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| D | aud_struct.h | 35 …volatile uint32_t samp_rate_adc : 2; //0x0[1:0],ADC采样率配置 0：8K 1：16K 2：44.1K …
36 volatile uint32_t dac_enable : 1; //0x0[2],DAC使能 1：使能,0,RW
37 volatile uint32_t adc_enable : 1; //0x0[3],ADC使能 1：使能,0,RW
38 volatile uint32_t dtmf_enable : 1; //0x0[4],DTMF使能 1: 使能,0,RW
39 volatile uint32_t line_enable : 1; //0x0[5],LINE IN使能 1：使能,0,RW
40 …volatile uint32_t samp_rate_dac : 2; //0x0[7:6],DAC采样率配置 0：8K 1：16K 2：44.1K …
41 volatile uint32_t reserved :24; //0x0[31:8],reserved,0,R
43 uint32_t v;
51 …volatile uint32_t tone_pattern : 1; //0x1[0],1：Tone1(Active_Time) + Tone2(Paus…
52 volatile uint32_t tone_mode : 1; //0x1[1],1：连续模式， 0：单次模式,0,RW
[all …]
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| D | aon_pmu_struct.h | 34 volatile uint32_t memchk_bps : 1; //0x0[0],memcheck bypass,1,R/W
35 volatile uint32_t reserved :31; //0x0[31:1],reserved,0,R
37 uint32_t v;
45 volatile uint32_t touch_select : 4; //0x1[3:0], ,None,R
46 volatile uint32_t touch_int_en :16; //0x1[19:4], ,None,R/W
47 volatile uint32_t usbplug_int_en : 1; //0x1[20], ,None,R/W
48 volatile uint32_t reserved :11; //0x1[31:21],reserved,0,R
50 uint32_t v;
58 volatile uint32_t wdt_rst_ana : 1; //0x2[0],wdt rst of ana,None,R/W
59 volatile uint32_t wdt_rst_top : 1; //0x2[1],wdt rst of top,None,R/W
[all …]
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| /device/soc/esp/esp32/components/soc/esp32/include/soc/ |
| D | slc_struct.h | 26 uint32_t slc0_tx_rst: 1;
27 uint32_t slc0_rx_rst: 1;
28 uint32_t ahbm_fifo_rst: 1;
29 uint32_t ahbm_rst: 1;
30 uint32_t slc0_tx_loop_test: 1;
31 uint32_t slc0_rx_loop_test: 1;
32 uint32_t slc0_rx_auto_wrback: 1;
33 uint32_t slc0_rx_no_restart_clr: 1;
34 uint32_t slc0_rxdscr_burst_en: 1;
35 uint32_t slc0_rxdata_burst_en: 1;
[all …]
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| D | host_struct.h | 24 uint32_t reserved_0;
25 uint32_t reserved_4;
26 uint32_t reserved_8;
27 uint32_t reserved_c;
30 uint32_t reserved0: 24;
31 uint32_t func2_int: 1;
32 uint32_t reserved25: 7;
34 uint32_t val;
38 uint32_t func2_int_en: 1;
39 uint32_t reserved1: 31;
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| D | spi_struct.h | 26 uint32_t reserved0: 16; /*reserved*/
27 …uint32_t flash_per: 1; /*program erase resume bit program erase suspend …
28 …uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend…
29 …uint32_t usr: 1; /*User define command enable. An operation will b…
30 …uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit…
31 …uint32_t flash_res: 1; /*This bit combined with reg_resandres bit release…
32 …uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will …
33 …uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be …
34 …uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operatio…
35 …uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation…
[all …]
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| D | rtc_cntl_struct.h | 26 …uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_…
27 …uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_…
28 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
29 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
30 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
31 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
32 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
33 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
34 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
35 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
[all …]
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| D | mcpwm_struct.h | 26 … uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
27 uint32_t reserved8: 24;
29 uint32_t val;
34 …uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE…
35 uint32_t period: 16; /*period shadow reg of PWM timer0*/
36 …uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1:…
37 uint32_t reserved26: 6;
39 uint32_t val;
43 …uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ …
44 …uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: dec…
[all …]
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| D | i2s_struct.h | 24 uint32_t reserved_0;
25 uint32_t reserved_4;
28 uint32_t tx_reset: 1;
29 uint32_t rx_reset: 1;
30 uint32_t tx_fifo_reset: 1;
31 uint32_t rx_fifo_reset: 1;
32 uint32_t tx_start: 1;
33 uint32_t rx_start: 1;
34 uint32_t tx_slave_mod: 1;
35 uint32_t rx_slave_mod: 1;
[all …]
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| D | emac_mac_struct.h | 29 …uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to th…
30 …uint32_t rx : 1; /*When this bit is set the receiver state machine of the MAC is enabl…
31 …uint32_t tx : 1; /*When this bit is set the transmit state machine of the MAC is enabl…
32 uint32_t deferralcheck : 1; /*Deferral Check.*/
33 …uint32_t backofflimit : 2; /*The Back-Off limit determines the random integer number (r) of slot …
34 …uint32_t padcrcstrip : 1; /*When this bit is set the MAC strips the Pad or FCS field on the inc…
35 uint32_t reserved8 : 1;
36 …uint32_t retry : 1; /*When this bit is set the MAC attempts only one transmission. When a…
37 …uint32_t rxipcoffload : 1; /*When this bit is set the MAC calculates the 16-bit one's complement…
38 …uint32_t duplex : 1; /*When this bit is set the MAC operates in the full-duplex mode where…
[all …]
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| D | uhci_struct.h | 26 … uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/
27 … uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/
28 uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/
29 … uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/
30 … uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/
31 … uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/
32 …uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next…
33 uint32_t out_no_restart_clr: 1; /*don't use*/
34 …uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all da…
35 …uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive d…
[all …]
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| D | sdmmc_struct.h | 26 uint32_t reserved1: 1;
27 uint32_t disable_int_on_completion: 1;
28 uint32_t last_descriptor: 1;
29 uint32_t first_descriptor: 1;
30 uint32_t second_address_chained: 1;
31 uint32_t end_of_ring: 1;
32 uint32_t reserved2: 24;
33 uint32_t card_error_summary: 1;
34 uint32_t owned_by_idmac: 1;
35 uint32_t buffer1_size: 13;
[all …]
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| D | uart_struct.h | 29 uint32_t val;
33 …uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver…
34 …uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amou…
35 …uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver…
36 …uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver…
37 …uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver…
38 …uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver…
39 …uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver…
40 …uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver…
41 …uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver…
[all …]
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| D | sens_struct.h | 26 uint32_t sar1_clk_div: 8;
27 uint32_t sar1_sample_cycle: 8;
28 uint32_t sar1_sample_bit: 2;
29 uint32_t sar1_clk_gated: 1;
30 uint32_t sar1_sample_num: 8;
31 …uint32_t sar1_dig_force: 1; /*1: ADC1 is controlled by the digital controller 0…
32 uint32_t sar1_data_inv: 1;
33 uint32_t reserved29: 3;
35 uint32_t val;
37 uint32_t sar_read_status1; /**/
[all …]
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| D | rtc_io_struct.h | 26 uint32_t reserved0: 14;
27 uint32_t data:18; /*GPIO0~17 output value*/
29 uint32_t val;
33 uint32_t reserved0: 14;
34 uint32_t w1ts:18; /*GPIO0~17 output value write 1 to set*/
36 uint32_t val;
40 uint32_t reserved0: 14;
41 uint32_t w1tc:18; /*GPIO0~17 output value write 1 to clear*/
43 uint32_t val;
47 uint32_t reserved0: 14;
[all …]
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| D | i2c_struct.h | 26 …uint32_t period:14; /*This register is used to configure the low level width of SCL c…
27 uint32_t reserved14: 18;
29 uint32_t val;
33 …uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of…
34 …uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of…
35 …uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this…
36 uint32_t reserved3: 1;
37 …uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clea…
38 … uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/
39 …uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data n…
[all …]
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| D | ledc_struct.h | 28 …uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to …
29 …uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channe…
30 …uint32_t idle_lv: 1; /*This bit is used to control the output value when high spee…
31 …uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reser…
32 uint32_t reserved4: 26;
33 …uint32_t clk_en: 1; /*This bit is clock gating control signal. when software conf…
35 uint32_t val;
39 …uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) sele…
40 uint32_t reserved20: 12;
42 uint32_t val;
[all …]
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| D | rmt_struct.h | 24 …uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fi…
30 …uint32_t div_cnt: 8; /*This register is used to configure the frequency divide…
31 …uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input si…
32 …uint32_t mem_size: 4; /*This register is used to configure the the amount of mem…
33 …uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for ch…
34 …uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is mo…
35 …uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:m…
36 …uint32_t clk_en: 1; /*This bit is used to control clock.when software config…
38 uint32_t val;
42 … uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/
[all …]
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| D | timer_group_struct.h | 27 uint32_t reserved0: 10;
28 uint32_t alarm_en: 1; /*When set alarm is enabled*/
29 …uint32_t level_int_en: 1; /*When set level type interrupt will be generated during al…
30 …uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during ala…
31 uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/
32 … uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/
33 …uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When clea…
34 … uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
36 uint32_t val;
38 …uint32_t cnt_low; /*Register to store timer 0/1 time-base counter curr…
[all …]
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| /device/soc/st/stm32f407zg/uniproton/board/common/ |
| D | stm32f4xx.h | 125 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
138 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
496 typedef uint32_t u32;
500 typedef const uint32_t uc32; /*!< Read Only */
504 typedef __IO uint32_t vu32;
508 typedef __I uint32_t vuc32; /*!< Read Only */
533 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
534 …__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ …
535 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
536 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
[all …]
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/driver/sys_ctrl/ |
| D | sys_driver.h | 62 uint32_t sys_drv_usb_analog_phy_en(bool ctrl, void *arg);
64 uint32_t sys_drv_usb_analog_speed_en(bool ctrl, void *arg);
66 uint32_t sys_drv_usb_analog_ckmcu_en(bool ctrl, void *arg);
77 void sys_drv_pwm_set_clock(uint32_t mode, uint32_t param);
87 void sys_drv_flash_cksel(uint32_t value);
89 void sys_drv_flash_set_clk_div(uint32_t value);
91 uint32_t sys_drv_flash_get_clk_sel(void);
93 uint32_t sys_drv_flash_get_clk_div(void);
95 void sys_drv_set_qspi_vddram_voltage(uint32_t param);
97 void sys_drv_set_qspi_io_voltage(uint32_t param);
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