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Searched refs:DPIO_CH0 (Results 1 – 5 of 5) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
Dhandlers.c3257 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3258 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3259 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3260 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3261 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3262 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3263 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
3265 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3266 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); in init_bxt_mmio_info()
3267 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c167 [DPIO_CH0] = { .port = PORT_B },
177 [DPIO_CH0] = { .port = PORT_A },
190 [DPIO_CH0] = { .port = PORT_B },
200 [DPIO_CH0] = { .port = PORT_A },
210 [DPIO_CH0] = { .port = PORT_C },
248 if (port == phy_info->channel[DPIO_CH0].port) { in bxt_port_to_phy_channel()
250 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
265 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
805 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
820 if (ch == DPIO_CH0) in chv_phy_pre_pll_enable()
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Dintel_display_power.c1531 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1532 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1533 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1539 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | in assert_chv_phy_status()
1540 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | in assert_chv_phy_status()
1541 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); in assert_chv_phy_status()
1547 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) in assert_chv_phy_status()
1548 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
1555 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1557 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
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Dintel_display_types.h1462 return DPIO_CH0; in vlv_dig_port_to_channel()
1490 return DPIO_CH0; in vlv_pipe_to_channel()
Dintel_display.h265 DPIO_CH0, enumerator