Searched refs:DPLL (Results 1 – 16 of 16) sorted by relevance
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
39 - reg : offsets for the register set for controlling the DPLL.
49 - DPLL mode setting - defining any one or more of the following overrides
51 - ti,low-power-stop : DPLL supports low power stop mode, gating output
52 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
53 - ti,lock : DPLL locks in programmed rate
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| D | apll.txt | 11 a subtype of a DPLL [2], although a simplified one at that.
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dvo.c | 494 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
495 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init()
503 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
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| D | intel_display.c | 1113 val = intel_de_read(dev_priv, DPLL(pipe)); in assert_pll()
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1405 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
1515 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1571 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
[all …]
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| D | intel_display_power.c | 1404 u32 val = intel_de_read(dev_priv, DPLL(pipe)); in vlv_display_power_well_init()
1410 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_display_power_well_init()
1566 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
5408 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); in chv_phy_control_init()
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| D | intel_dp.c | 827 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos5422-odroid-core.dtsi | 97 /* derived from 600MHz DPLL */
199 /* derived from 600MHz DPLL */
235 /* derived from 600MHz DPLL */
247 /* derived from 600MHz DPLL */
262 /* derived from 600MHz DPLL */
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| D | rk3036.dtsi | 217 * Fix the emac parent clock is DPLL instead of APLL.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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| /kernel/linux/linux-5.10/Documentation/arm/omap/ |
| D | dss.rst | 32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| D | reg.h | 256 #define DPLL 0x034A macro
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| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/hamradio/ |
| D | z8530drv.rst | 308 present at all (BayCom). It feeds back the output of the DPLL
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 3419 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/ |
| D | 0009_linux_sound.patch | 15210 /* DPLL lock information */
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