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Searched refs:GICR_ICENABLER0 (Results 1 – 4 of 4) sorted by relevance

/kernel/liteos_a/arch/arm/gic/
Dgic_v3.c259 GIC_REG_32(GICR_ICENABLER0(i)) = mask; in HalIrqMask()
334 GIC_REG_32(GICR_ICENABLER0(cpu)) = 0xffffffff; in HalIrqInitPercpu()
/kernel/liteos_a/arch/arm/include/
Dgic_v3.h95 #define GICR_ICENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0180) macro
/kernel/linux/linux-5.10/include/linux/irqchip/
Darm-gic-v3.h230 #define GICR_ICENABLER0 GICD_ICENABLER macro
/kernel/linux/linux-5.10/arch/arm64/kvm/vgic/
Dvgic-mmio-v3.c637 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0,