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Searched refs:Reset (Results 1 – 25 of 279) sorted by relevance

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/kernel/linux/linux-5.10/drivers/reset/
DKconfig6 bool "Reset Controller Support"
9 Generic Reset Controller support.
19 tristate "Altera Arria10 System Resource Reset"
26 bool "AR71xx Reset Driver" if COMPILE_TEST
33 bool "AXS10x Reset Driver" if COMPILE_TEST
39 bool "Berlin Reset Driver" if COMPILE_TEST
62 bool "Synopsys HSDK Reset Driver"
69 tristate "i.MX7/8 Reset Driver"
78 bool "Intel Reset Controller Driver"
88 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
[all …]
/kernel/linux/linux-5.10/Documentation/hwmon/
Dltc3815.rst44 in1_reset_history Reset input voltage history.
50 in2_reset_history Reset output voltage history.
55 temp1_reset_history Reset temperature history.
60 curr1_reset_history Reset input current history.
66 curr2_reset_history Reset output current history.
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Daspeed-wdt.txt16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
26 Reset types:
28 - cpu: Reset CPU on watchdog timeout
30 - soc: Reset 'System on Chip' on watchdog timeout
32 - system: Reset system on watchdog timeout
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dnxp,lpc1850-rgu.txt1 NXP LPC1850 Reset Generation Unit (RGU)
18 Reset Peripheral
64 Reset provider example:
73 Reset consumer example:
Dzynq-reset.txt1 Xilinx Zynq Reset Manager
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
24 Reset outputs:
Dti-syscon-reset.txt1 TI SysCon Reset Controller
12 A SysCon Reset Controller node defines a device that uses a syscon node
16 SysCon Reset Controller Node
49 SysCon Reset Consumer Nodes
Dreset.txt1 = Reset Signal Device Tree Bindings =
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
32 = Reset providers =
45 = Reset consumers =
Dti,sci-reset.txt1 Texas Instruments System Control Interface (TI-SCI) Reset Controller
12 TI-SCI Reset Controller Node
24 TI-SCI Reset Consumer Nodes
Dst,stm32mp1-rcc.txt1 STMicroelectronics STM32MP1 Peripheral Reset Controller
Dst,stm32-rcc.txt1 STMicroelectronics STM32 Peripheral Reset Controller
/kernel/liteos_a/kernel/extended/blackbox/
Dlos_blackbox_system_adapter.c150 static void Reset(struct ErrorInfo *info) in Reset() function
224 .Reset = NULL, in BBoxTest()
242 .Reset = Reset, in OsBBoxSystemAdapterInit()
Dlos_blackbox_core.c151 if (ops->ops.Reset != NULL) { in InvokeModuleOps()
153 ops->ops.Reset(info); in InvokeModuleOps()
235 if (ops->ops.Dump == NULL && ops->ops.Reset == NULL) { in SaveLogWithoutReset()
335 … ops->ops.module, ops->ops.Dump, ops->ops.Reset, ops->ops.GetLastLogInfo, ops->ops.SaveLastLog); in PrintModuleOps()
/kernel/linux/linux-5.10/drivers/reset/hisilicon/
DKconfig3 tristate "Hi3660 Reset Driver"
10 tristate "Hi6220 Reset Driver"
/kernel/linux/linux-5.10/init/
Dinitramfs.c191 Reset enumerator
327 next_state = Reset; in do_name()
399 next_state = Reset; in do_symlink()
411 [Reset] = do_reset,
440 state = Reset; in flush_buffer()
500 if (state != Reset) in unpack_to_rootfs()
/kernel/linux/linux-5.10/Documentation/driver-api/mmc/
Dmmc-tools.rst26 - Permanently enable the eMMC H/W Reset feature.
27 - Permanently disable the eMMC H/W Reset feature.
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dnvidia,tegra210-car.txt1 NVIDIA Tegra210 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
Dnvidia,tegra30-car.txt1 NVIDIA Tegra30 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
Dnvidia,tegra114-car.txt1 NVIDIA Tegra114 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
Dnvidia,tegra20-car.txt1 NVIDIA Tegra20 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Daltera-a10sr.txt20 a10sr_rst Reset Controller
30 Arria10 Peripheral PHY Reset
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/nfc/
Dnfcmrvl.txt57 /* Reset IO */
81 /* Reset IO */
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-papr-pmem48 * "CtlResCt" : Controller Reset Count
49 * "CtlResTm" : Controller Reset Elapsed Time
Dsysfs-bus-usb-lvstest32 Write to this node to issue "Reset" for Link Layer Validation
58 Write to this node to issue "Warm Reset" for Link Layer Validation
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/
Dbrcm,bcm21664-resetmgr.txt1 Broadcom Kona Family Reset Manager
Dkeystone-reset.txt7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.

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