Searched refs:Reset (Results 1 – 25 of 279) sorted by relevance
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/kernel/linux/linux-5.10/drivers/reset/ |
D | Kconfig | 6 bool "Reset Controller Support" 9 Generic Reset Controller support. 19 tristate "Altera Arria10 System Resource Reset" 26 bool "AR71xx Reset Driver" if COMPILE_TEST 33 bool "AXS10x Reset Driver" if COMPILE_TEST 39 bool "Berlin Reset Driver" if COMPILE_TEST 62 bool "Synopsys HSDK Reset Driver" 69 tristate "i.MX7/8 Reset Driver" 78 bool "Intel Reset Controller Driver" 88 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST [all …]
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/kernel/linux/linux-5.10/Documentation/hwmon/ |
D | ltc3815.rst | 44 in1_reset_history Reset input voltage history. 50 in2_reset_history Reset output voltage history. 55 temp1_reset_history Reset temperature history. 60 curr1_reset_history Reset input current history. 66 curr2_reset_history Reset output current history.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/ |
D | aspeed-wdt.txt | 16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed 26 Reset types: 28 - cpu: Reset CPU on watchdog timeout 30 - soc: Reset 'System on Chip' on watchdog timeout 32 - system: Reset system on watchdog timeout
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
D | nxp,lpc1850-rgu.txt | 1 NXP LPC1850 Reset Generation Unit (RGU) 18 Reset Peripheral 64 Reset provider example: 73 Reset consumer example:
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D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager 14 The Zynq Reset Manager needs to be a childnode of the SLCR. 24 Reset outputs:
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D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller 12 A SysCon Reset Controller node defines a device that uses a syscon node 16 SysCon Reset Controller Node 49 SysCon Reset Consumer Nodes
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D | reset.txt | 1 = Reset Signal Device Tree Bindings = 4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole 32 = Reset providers = 45 = Reset consumers =
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D | ti,sci-reset.txt | 1 Texas Instruments System Control Interface (TI-SCI) Reset Controller 12 TI-SCI Reset Controller Node 24 TI-SCI Reset Consumer Nodes
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D | st,stm32mp1-rcc.txt | 1 STMicroelectronics STM32MP1 Peripheral Reset Controller
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D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Peripheral Reset Controller
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/kernel/liteos_a/kernel/extended/blackbox/ |
D | los_blackbox_system_adapter.c | 150 static void Reset(struct ErrorInfo *info) in Reset() function 224 .Reset = NULL, in BBoxTest() 242 .Reset = Reset, in OsBBoxSystemAdapterInit()
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D | los_blackbox_core.c | 151 if (ops->ops.Reset != NULL) { in InvokeModuleOps() 153 ops->ops.Reset(info); in InvokeModuleOps() 235 if (ops->ops.Dump == NULL && ops->ops.Reset == NULL) { in SaveLogWithoutReset() 335 … ops->ops.module, ops->ops.Dump, ops->ops.Reset, ops->ops.GetLastLogInfo, ops->ops.SaveLastLog); in PrintModuleOps()
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/kernel/linux/linux-5.10/drivers/reset/hisilicon/ |
D | Kconfig | 3 tristate "Hi3660 Reset Driver" 10 tristate "Hi6220 Reset Driver"
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/kernel/linux/linux-5.10/init/ |
D | initramfs.c | 191 Reset enumerator 327 next_state = Reset; in do_name() 399 next_state = Reset; in do_symlink() 411 [Reset] = do_reset, 440 state = Reset; in flush_buffer() 500 if (state != Reset) in unpack_to_rootfs()
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/kernel/linux/linux-5.10/Documentation/driver-api/mmc/ |
D | mmc-tools.rst | 26 - Permanently enable the eMMC H/W Reset feature. 27 - Permanently disable the eMMC H/W Reset feature.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
D | nvidia,tegra210-car.txt | 1 NVIDIA Tegra210 Clock And Reset Controller 6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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D | nvidia,tegra30-car.txt | 1 NVIDIA Tegra30 Clock And Reset Controller 6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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D | nvidia,tegra114-car.txt | 1 NVIDIA Tegra114 Clock And Reset Controller 6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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D | nvidia,tegra20-car.txt | 1 NVIDIA Tegra20 Clock And Reset Controller 6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
D | altera-a10sr.txt | 20 a10sr_rst Reset Controller 30 Arria10 Peripheral PHY Reset
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/nfc/ |
D | nfcmrvl.txt | 57 /* Reset IO */ 81 /* Reset IO */
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/kernel/linux/linux-5.10/Documentation/ABI/testing/ |
D | sysfs-bus-papr-pmem | 48 * "CtlResCt" : Controller Reset Count 49 * "CtlResTm" : Controller Reset Elapsed Time
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D | sysfs-bus-usb-lvstest | 32 Write to this node to issue "Reset" for Link Layer Validation 58 Write to this node to issue "Warm Reset" for Link Layer Validation
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/ |
D | brcm,bcm21664-resetmgr.txt | 1 Broadcom Kona Family Reset Manager
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D | keystone-reset.txt | 7 SoC. Each watchdog timer event input is connected to the Reset Mux 8 block. The Reset Mux block can be configured to cause reset or not.
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