Searched refs:aeqe (Results 1 – 7 of 7) sorted by relevance
/kernel/linux/linux-5.10/drivers/infiniband/hw/hns/ |
D | hns_roce_hw_v1.c | 3614 struct hns_roce_aeqe *aeqe, int qpn) in hns_roce_v1_wq_catas_err_handle() argument 3619 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M, in hns_roce_v1_wq_catas_err_handle() 3648 struct hns_roce_aeqe *aeqe, in hns_roce_v1_local_wq_access_err_handle() argument 3654 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M, in hns_roce_v1_local_wq_access_err_handle() 3683 struct hns_roce_aeqe *aeqe, in hns_roce_v1_qp_err_handle() argument 3690 qpn = roce_get_field(aeqe->event.qp_event.qp, in hns_roce_v1_qp_err_handle() 3693 phy_port = roce_get_field(aeqe->event.qp_event.qp, in hns_roce_v1_qp_err_handle() 3705 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn); in hns_roce_v1_qp_err_handle() 3708 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn); in hns_roce_v1_qp_err_handle() 3718 struct hns_roce_aeqe *aeqe, in hns_roce_v1_cq_err_handle() argument [all …]
|
D | hns_roce_hw_v2.c | 5480 struct hns_roce_aeqe *aeqe; in next_aeqe_sw_v2() local 5482 aeqe = hns_roce_buf_offset(eq->mtr.kmem, in next_aeqe_sw_v2() 5486 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ in next_aeqe_sw_v2() 5487 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; in next_aeqe_sw_v2() 5494 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); in hns_roce_v2_aeq_int() local 5502 while (aeqe) { in hns_roce_v2_aeq_int() 5508 event_type = roce_get_field(aeqe->asyn, in hns_roce_v2_aeq_int() 5511 sub_type = roce_get_field(aeqe->asyn, in hns_roce_v2_aeq_int() 5514 qpn = roce_get_field(aeqe->event.qp_event.qp, in hns_roce_v2_aeq_int() 5517 cqn = roce_get_field(aeqe->event.cq_event.cq, in hns_roce_v2_aeq_int() [all …]
|
/kernel/linux/linux-5.10/drivers/crypto/hisilicon/ |
D | qm.c | 80 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1) argument 706 struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head; in qm_aeq_irq() local 713 while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) { in qm_aeq_irq() 714 type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT; in qm_aeq_irq() 724 aeqe = qm->aeqe; in qm_aeq_irq() 727 aeqe++; in qm_aeq_irq() 1381 } else if (qm->aeqe && !strcmp(name, "AEQE")) { in qm_eq_aeq_dump() 1382 xeqe = qm->aeqe + xeqe_id; in qm_eq_aeq_dump() 2373 QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH); in hisi_qm_memory_init()
|
D | qm.h | 219 struct qm_aeqe *aeqe; member
|
/kernel/linux/linux-5.10/drivers/net/ethernet/huawei/hinic/ |
D | hinic_hw_eqs.c | 594 struct hinic_aeq_elem *aeqe; in aeq_elements_init() local 598 aeqe = GET_AEQ_ELEM(eq, i); in aeq_elements_init() 599 aeqe->desc = cpu_to_be32(init_val); in aeq_elements_init()
|
/kernel/linux/linux-5.10/drivers/infiniband/hw/bnxt_re/ |
D | main.c | 867 void *aeqe, void *obj) in bnxt_re_aeq_handler() argument 874 type = ((struct creq_base *)aeqe)->type; in bnxt_re_aeq_handler() 876 unaffi_async = aeqe; in bnxt_re_aeq_handler() 879 affi_async = aeqe; in bnxt_re_aeq_handler()
|
/kernel/linux/linux-5.10/drivers/infiniband/hw/i40iw/ |
D | i40iw_ctrl.c | 1863 u64 *aeqe; in i40iw_sc_get_next_aeqe() local 1868 aeqe = (u64 *)I40IW_GET_CURRENT_AEQ_ELEMENT(aeq); in i40iw_sc_get_next_aeqe() 1869 get_64bit_val(aeqe, 0, &compl_ctx); in i40iw_sc_get_next_aeqe() 1870 get_64bit_val(aeqe, 8, &temp); in i40iw_sc_get_next_aeqe() 1876 i40iw_debug_buf(aeq->dev, I40IW_DEBUG_WQE, "AEQ_ENTRY", aeqe, 16); in i40iw_sc_get_next_aeqe()
|