| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx8mp.c | 427 void __iomem *anatop_base, *ccm_base; in imx8mp_clocks_probe() local
436 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
437 if (WARN_ON(IS_ERR(ccm_base))) { in imx8mp_clocks_probe()
439 return PTR_ERR(ccm_base); in imx8mp_clocks_probe()
550 …hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0… in imx8mp_clocks_probe()
553 …hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080… in imx8mp_clocks_probe()
554 …hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100… in imx8mp_clocks_probe()
555 …GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180); in imx8mp_clocks_probe()
556 …R_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200); in imx8mp_clocks_probe()
557 …hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base + 0x… in imx8mp_clocks_probe()
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| D | clk-vf610.c | 14 #define CCM_CCR (ccm_base + 0x00)
15 #define CCM_CSR (ccm_base + 0x04)
16 #define CCM_CCSR (ccm_base + 0x08)
17 #define CCM_CACRR (ccm_base + 0x0c)
18 #define CCM_CSCMR1 (ccm_base + 0x10)
19 #define CCM_CSCDR1 (ccm_base + 0x14)
20 #define CCM_CSCDR2 (ccm_base + 0x18)
21 #define CCM_CSCDR3 (ccm_base + 0x1c)
22 #define CCM_CSCMR2 (ccm_base + 0x20)
23 #define CCM_CSCDR4 (ccm_base + 0x24)
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| D | clk-imx5.c | 30 #define MXC_CCM_CCR (ccm_base + 0x00)
31 #define MXC_CCM_CCDR (ccm_base + 0x04)
32 #define MXC_CCM_CSR (ccm_base + 0x08)
33 #define MXC_CCM_CCSR (ccm_base + 0x0c)
34 #define MXC_CCM_CACRR (ccm_base + 0x10)
35 #define MXC_CCM_CBCDR (ccm_base + 0x14)
36 #define MXC_CCM_CBCMR (ccm_base + 0x18)
37 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
38 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)
39 #define MXC_CCM_CSCDR1 (ccm_base + 0x24)
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| D | clk.c | 37 void imx_mmdc_mask_handshake(void __iomem *ccm_base, in imx_mmdc_mask_handshake() argument
42 reg = readl_relaxed(ccm_base + CCM_CCDR); in imx_mmdc_mask_handshake()
44 writel_relaxed(reg, ccm_base + CCM_CCDR); in imx_mmdc_mask_handshake()
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| D | clk-imx6sl.c | 101 static void __iomem *ccm_base; variable
128 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
169 saved_arm_div = readl_relaxed(ccm_base + CACRR); in imx6sl_set_wait_clk()
170 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); in imx6sl_set_wait_clk()
172 writel_relaxed(saved_arm_div, ccm_base + CACRR); in imx6sl_set_wait_clk()
174 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) in imx6sl_set_wait_clk()
290 ccm_base = base; in imx6sl_clocks_init()
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| D | clk-imx6q.c | 266 static void mmdc_ch1_disable(void __iomem *ccm_base) in mmdc_ch1_disable() argument
274 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_disable()
276 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_disable()
279 static void mmdc_ch1_reenable(void __iomem *ccm_base) in mmdc_ch1_reenable() argument
284 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
286 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
318 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) in init_ldb_clks() argument
324 reg = readl_relaxed(ccm_base + CCM_CS2CDR); in init_ldb_clks()
366 mmdc_ch1_disable(ccm_base); in init_ldb_clks()
369 reg = readl_relaxed(ccm_base + CCM_CS2CDR); in init_ldb_clks()
[all …]
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| D | clk-imx25.c | 41 #define ccm(x) (ccm_base + (x))
76 static int __init __mx25_clocks_init(void __iomem *ccm_base) in __mx25_clocks_init() argument
78 BUG_ON(!ccm_base); in __mx25_clocks_init()
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| D | clk.h | 22 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
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| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | pm-imx6.c | 62 static void __iomem *ccm_base; variable
225 struct imx6_pm_base ccm_base; member
234 u32 val = readl_relaxed(ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
239 writel_relaxed(val, ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
253 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
256 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
259 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
262 writel(val, ccm_base + CCR); in imx6_enable_rbc()
280 val = readl_relaxed(ccm_base + CLPCR); in imx6q_enable_wb()
283 writel_relaxed(val, ccm_base + CLPCR); in imx6q_enable_wb()
[all …]
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| D | pm-imx27.c | 19 void __iomem *ccm_base; in mx27_suspend_enter() local
24 ccm_base = of_iomap(np, 0); in mx27_suspend_enter()
25 BUG_ON(!ccm_base); in mx27_suspend_enter()
30 cscr = imx_readl(ccm_base); in mx27_suspend_enter()
32 imx_writel(cscr, ccm_base); in mx27_suspend_enter()
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| D | cpu-imx27.c | 25 void __iomem *ccm_base; in mx27_read_cpu_rev() local
30 ccm_base = of_iomap(np, 0); in mx27_read_cpu_rev()
31 BUG_ON(!ccm_base); in mx27_read_cpu_rev()
37 val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID); in mx27_read_cpu_rev()
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| D | pm-imx5.c | 133 static void __iomem *ccm_base; variable
152 ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()
194 imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); in mx5_cpu_lp_set()
388 ccm_base = ioremap(data->ccm_addr, SZ_16K); in imx5_pm_common_init()
391 WARN_ON(!ccm_base || !cortex_base || !gpc_base); in imx5_pm_common_init()
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