| /kernel/linux/linux-5.10/arch/m68k/ifpsp060/ |
| D | pfpsp.sa | 1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
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| D | itest.sa | 1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
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| D | fplsp.sa | 1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
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| D | ftest.sa | 1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
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| D | ilsp.sa | 1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.h | 32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *dc,
51 struct dc *dc,
54 struct dc *dc,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
59 struct dc *dc,
[all …]
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| D | dcn10_hw_sequencer.c | 77 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
86 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
94 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
108 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); in dcn10_lock_all_pipes()
110 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); in dcn10_lock_all_pipes()
114 static void log_mpc_crc(struct dc *dc, in log_mpc_crc() argument
117 struct dc_context *dc_ctx = dc->ctx; in log_mpc_crc()
118 struct dce_hwseq *hws = dc->hwseq; in log_mpc_crc()
128 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx) in dcn10_log_hubbub_state() argument
130 struct dc_context *dc_ctx = dc->ctx; in dcn10_log_hubbub_state()
[all …]
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| /kernel/linux/linux-5.10/drivers/dma/ |
| D | txx9dmac.c | 24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39 #define channel64_readl(dc, name) \ argument
40 __raw_readl(&(__dma_regs(dc)->name))
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 53 void (*init_hw)(struct dc *dc);
54 void (*power_down_on_boot)(struct dc *dc);
55 void (*enable_accelerated_mode)(struct dc *dc,
57 enum dc_status (*apply_ctx_to_hw)(struct dc *dc,
59 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
60 void (*apply_ctx_for_surface)(struct dc *dc,
63 void (*program_front_end_for_ctx)(struct dc *dc,
65 bool (*disconnect_pipes)(struct dc *dc,
67 void (*wait_for_pending_cleared)(struct dc *dc,
69 void (*post_unlock_program_front_end)(struct dc *dc,
[all …]
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| D | hw_sequencer_private.h | 72 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
73 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
74 void (*init_pipes)(struct dc *dc, struct dc_state *context);
75 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
76 void (*update_plane_addr)(const struct dc *dc,
78 void (*plane_atomic_disconnect)(struct dc *dc,
80 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
81 bool (*set_input_transfer_func)(struct dc *dc,
84 bool (*set_output_transfer_func)(struct dc *dc,
87 void (*power_down)(struct dc *dc);
[all …]
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| /kernel/linux/linux-5.10/drivers/tty/ |
| D | nozomi.c | 335 struct nozomi *dc; member
492 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
494 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
501 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
502 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
503 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
504 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
505 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
506 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
507 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.h | 36 struct dc *dc,
39 struct dc *dc,
41 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
42 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
43 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
45 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 void dcn20_program_output_csc(struct dc *dc,
55 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
57 struct dc *dc,
61 struct dc *dc,
[all …]
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| D | dcn20_resource.h | 34 struct dc;
43 struct dc *dc);
53 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
59 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
68 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
101 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
116 struct dc *dc,
120 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
122 struct dc *dc,
130 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 74 dc->ctx
77 dc->ctx->logger
140 static void destroy_links(struct dc *dc) in destroy_links() argument
144 for (i = 0; i < dc->link_count; i++) { in destroy_links()
145 if (NULL != dc->links[i]) in destroy_links()
146 link_destroy(&dc->links[i]); in destroy_links()
151 struct dc *dc, in create_links() argument
156 struct dc_bios *bios = dc->ctx->dc_bios; in create_links()
158 dc->link_count = 0; in create_links()
180 link_init_params.ctx = dc->ctx; in create_links()
[all …]
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| D | dc_stream.c | 37 #define DC_LOGGER dc->ctx->logger
50 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
242 struct dc *dc = stream->ctx->dc; in dc_stream_get_status() local
243 return dc_stream_get_status_from_state(dc->current_state, stream); in dc_stream_get_status()
254 struct dc *dc; in dc_optimize_timing_for_fsft() local
256 dc = pStream->ctx->dc; in dc_optimize_timing_for_fsft()
258 return (dc->hwss.optimize_timing_for_fsft && in dc_optimize_timing_for_fsft()
259 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); in dc_optimize_timing_for_fsft()
272 struct dc *dc; in dc_stream_set_cursor_attributes() local
293 dc = stream->ctx->dc; in dc_stream_set_cursor_attributes()
[all …]
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| /kernel/linux/linux-5.10/drivers/md/bcache/ |
| D | writeback.c | 30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
48 div64_u64(bdev_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT, in __calc_target_rate()
52 div_u64(cache_sectors * dc->writeback_percent, 100); in __calc_target_rate()
61 static void __update_writeback_rate(struct cached_dev *dc) in __update_writeback_rate() argument
83 int64_t target = __calc_target_rate(dc); in __update_writeback_rate()
84 int64_t dirty = bcache_dev_sectors_dirty(&dc->disk); in __update_writeback_rate()
87 div_s64(error, dc->writeback_rate_p_term_inverse); in __update_writeback_rate()
91 if ((error < 0 && dc->writeback_rate_integral > 0) || in __update_writeback_rate()
93 dc->writeback_rate.next + NSEC_PER_MSEC))) { in __update_writeback_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/md/ |
| D | dm-delay.c | 53 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
55 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
58 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
60 mutex_lock(&dc->timer_lock); in queue_timeout()
62 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout()
63 mod_timer(&dc->delay_timer, expires); in queue_timeout()
65 mutex_unlock(&dc->timer_lock); in queue_timeout()
80 static struct bio *flush_delayed_bios(struct delay_c *dc, int flush_all) in flush_delayed_bios() argument
88 list_for_each_entry_safe(delayed, next, &dc->delayed_bios, list) { in flush_delayed_bios()
107 queue_timeout(dc, next_expires); in flush_delayed_bios()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 285 void dc_commit_updates_for_stream(struct dc *dc,
294 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
296 uint8_t dc_get_current_stream_count(struct dc *dc);
297 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
323 struct dc *dc,
328 struct dc *dc,
334 const struct dc *dc,
340 const struct dc *dc,
346 const struct dc *dc,
351 const struct dc *dc,
[all …]
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| D | dc.h | 263 struct dc;
269 bool (*get_dcc_compression_cap)(const struct dc *dc,
382 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
383 dm_get_timestamp(dc->ctx) : 0
386 if (dc->debug.bw_val_profile.enable) \
387 dc->debug.bw_val_profile.total_count++
390 if (dc->debug.bw_val_profile.enable) { \
392 voltage_level_tick = dm_get_timestamp(dc->ctx); \
393 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
397 if (dc->debug.bw_val_profile.enable) \
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 40 dc->ctx->logger
317 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
332 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
453 const struct dc *dc, in dcn_bw_calc_rq_dlg_ttu() argument
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu()
494 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
503 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; in dcn_bw_calc_rq_dlg_ttu()
636 static bool dcn_bw_apply_registry_override(struct dc *dc) in dcn_bw_apply_registry_override() argument
641 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns in dcn_bw_apply_registry_override()
642 && dc->debug.sr_exit_time_ns) { in dcn_bw_apply_registry_override()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | dc.c | 43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
48 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
91 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
114 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 62 dc->ctx->logger
95 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
142 bool dcn30_set_input_transfer_func(struct dc *dc, in dcn30_set_input_transfer_func() argument
146 struct dce_hwseq *hws = dc->hwseq; in dcn30_set_input_transfer_func()
185 bool dcn30_set_output_transfer_func(struct dc *dc, in dcn30_set_output_transfer_func() argument
190 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
218 struct dc *dc, in dcn30_set_writeback() argument
228 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
229 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
233 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
[all …]
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| D | dcn30_hwseq.h | 31 struct dc;
33 void dcn30_init_hw(struct dc *dc);
35 struct dc *dc,
39 struct dc *dc,
43 struct dc *dc,
47 struct dc *dc,
51 struct dc *dc,
58 bool dcn30_set_input_transfer_func(struct dc *dc,
61 bool dcn30_set_output_transfer_func(struct dc *dc,
68 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
|
| /kernel/linux/linux-5.10/drivers/scsi/esas2r/ |
| D | esas2r_disc.c | 291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/mvebu/ |
| D | dove-divider.c | 51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
[all …]
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