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Searched refs:fb_div (Results 1 – 25 of 25) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pll.c85 unsigned *fb_div, unsigned *ref_div) in amdgpu_pll_get_fb_ref_div() argument
92 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
95 if (*fb_div > fb_div_max) { in amdgpu_pll_get_fb_ref_div()
96 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); in amdgpu_pll_get_fb_ref_div()
97 *fb_div = fb_div_max; in amdgpu_pll_get_fb_ref_div()
125 unsigned fb_div_min, fb_div_max, fb_div; in amdgpu_pll_compute() local
202 ref_div_max, &fb_div, &ref_div); in amdgpu_pll_compute()
203 diff = abs(target_clock - (pll->reference_freq * fb_div) / in amdgpu_pll_compute()
217 &fb_div, &ref_div); in amdgpu_pll_compute()
221 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in amdgpu_pll_compute()
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Datombios_crtc.c583 u32 fb_div, in amdgpu_atombios_crtc_program_pll() argument
610 args.v1.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
620 args.v2.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
630 args.v3.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
647 args.v5.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
677 args.v6.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
826 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
855 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
862 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
868 u32 amount = (((fb_div * 10) + frac_fb_div) * in amdgpu_atombios_crtc_set_pll()
Damdgpu_atombios.h41 u32 fb_div; member
66 u32 fb_div; member
Dsi.c1615 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; in si_calc_upll_dividers() local
1618 do_div(fb_div, ref_freq); in si_calc_upll_dividers()
1621 if (fb_div > fb_mask) in si_calc_upll_dividers()
1624 fb_div &= fb_mask; in si_calc_upll_dividers()
1643 *optimal_fb_div = fb_div; in si_calc_upll_dividers()
1661 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
1679 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
1708 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
1713 if (fb_div < 307200) in si_set_uvd_clocks()
1784 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; in si_set_vce_clocks() local
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Datombios_crtc.h49 u32 fb_div,
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
45 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_engine_clock()
46 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; in radeon_legacy_get_engine_clock()
47 fb_div <<= 1; in radeon_legacy_get_engine_clock()
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
56 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
75 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_memory_clock()
76 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; in radeon_legacy_get_memory_clock()
77 fb_div <<= 1; in radeon_legacy_get_memory_clock()
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Dradeon_display.c934 unsigned *fb_div, unsigned *ref_div) in avivo_get_fb_ref_div() argument
941 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
944 if (*fb_div > fb_div_max) { in avivo_get_fb_ref_div()
945 *ref_div = (*ref_div * fb_div_max)/(*fb_div); in avivo_get_fb_ref_div()
946 *fb_div = fb_div_max; in avivo_get_fb_ref_div()
974 unsigned fb_div_min, fb_div_max, fb_div; in radeon_compute_pll_avivo() local
1054 ref_div_max, &fb_div, &ref_div); in radeon_compute_pll_avivo()
1055 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1069 &fb_div, &ref_div); in radeon_compute_pll_avivo()
1073 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in radeon_compute_pll_avivo()
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Drs780_dpm.c88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
406 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) in rs780_force_fbdiv() argument
415 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
417 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
460 rs780_force_fbdiv(rdev, max_dividers.fb_div); in rs780_set_engine_clock_scaling()
462 if (max_dividers.fb_div > min_dividers.fb_div) { in rs780_set_engine_clock_scaling()
464 MIN_FEEDBACK_DIV(min_dividers.fb_div) | in rs780_set_engine_clock_scaling()
465 MAX_FEEDBACK_DIV(max_dividers.fb_div), in rs780_set_engine_clock_scaling()
1049 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1056 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
Dradeon_uvd.c978 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; in radeon_uvd_calc_upll_dividers() local
981 do_div(fb_div, ref_freq); in radeon_uvd_calc_upll_dividers()
984 if (fb_div > fb_mask) in radeon_uvd_calc_upll_dividers()
987 fb_div &= fb_mask; in radeon_uvd_calc_upll_dividers()
1006 *optimal_fb_div = fb_div; in radeon_uvd_calc_upll_dividers()
Datombios_crtc.c829 u32 fb_div, in atombios_crtc_program_pll() argument
856 args.v1.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
866 args.v2.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
876 args.v3.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
893 args.v5.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
922 args.v6.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
1071 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1103 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1106 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1109 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
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Drv730_dpm.c159 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); in rv730_populate_mclk_value()
173 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); in rv730_populate_mclk_value()
Drv770.c53 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
73 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
77 fb_div |= 1; in rv770_set_uvd_clocks()
107 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
Dradeon_mode.h592 u32 fb_div; member
617 u32 fb_div; member
Dradeon_legacy_crtc.c267 uint16_t fb_div) in radeon_compute_pll_gain() argument
274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
Dni_dpm.c2095 u32 fb_div; in ni_init_smc_spll_table() local
2116 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in ni_init_smc_spll_table()
2120 fb_div &= ~0x00001FFF; in ni_init_smc_spll_table()
2121 fb_div >>= 1; in ni_init_smc_spll_table()
2130 if (fb_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in ni_init_smc_spll_table()
2139 …tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in ni_init_smc_spll_table()
Dsi.c6999 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
7017 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7046 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
7051 if (fb_div < 307200) in si_set_uvd_clocks()
7511 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; in si_set_vce_clocks() local
7532 &fb_div, &evclk_div, &ecclk_div); in si_set_vce_clocks()
7564 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK); in si_set_vce_clocks()
Dr600.c205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
234 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
239 fb_div >>= 1; in r600_set_uvd_clocks()
241 fb_div |= 1; in r600_set_uvd_clocks()
257 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
Dsi_dpm.c2834 u32 fb_div, p_div; in si_init_smc_spll_table() local
2854 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2858 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2859 fb_div >>= 1; in si_init_smc_spll_table()
2864 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2874 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()
Drv6xx_dpm.c529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
607 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); in rv6xx_program_mclk_stepping_entry()
Devergreen.c1195 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1214 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1241 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
1246 if (fb_div < 307200) in evergreen_set_uvd_clocks()
Dradeon_atombios.c2862 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2876 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2883 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; in radeon_atom_get_clock_dividers()
Dci_dpm.c3166 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c653 struct fixed31_32 fb_div; in calculate_ss() local
673 fb_div = dc_fixpt_from_fraction( in calculate_ss()
675 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); in calculate_ss()
681 fb_div, dc_fixpt_from_fraction(ss_data->percentage, in calculate_ss()
/kernel/linux/linux-5.10/drivers/video/fbdev/aty/
Dradeon_base.c1538 int fb_div, pll_output_freq = 0; in radeon_calc_pll_regs() local
1627 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1630 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1633 pr_debug("fb_div = 0x%x\n", fb_div); in radeon_calc_pll_regs()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/
Dsi_dpm.c2932 u32 fb_div, p_div; in si_init_smc_spll_table() local
2951 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2955 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2956 fb_div >>= 1; in si_init_smc_spll_table()
2961 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2971 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()