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Searched refs:gate (Results 1 – 25 of 353) sorted by relevance

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/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-periph-gate.c19 #define read_enb(gate) \ argument
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \ argument
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \ argument
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
26 #define read_rst(gate) \ argument
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
28 #define write_rst_clr(val, gate) \ argument
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
[all …]
/kernel/linux/linux-5.10/drivers/clk/mmp/
Dclk-gate.c29 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); in mmp_clk_gate_enable() local
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
43 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
45 if (gate->flags & MMP_CLK_GATE_NEED_DELAY) { in mmp_clk_gate_enable()
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-gate2.c42 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_enable() local
47 spin_lock_irqsave(gate->lock, flags); in clk_gate2_enable()
49 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
52 if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) { in clk_gate2_enable()
55 reg = readl(gate->reg); in clk_gate2_enable()
56 reg &= ~(3 << gate->bit_idx); in clk_gate2_enable()
57 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
58 writel(reg, gate->reg); in clk_gate2_enable()
62 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_enable()
69 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_disable() local
[all …]
Dclk-gate-exclusive.c25 struct clk_gate gate; member
31 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_exclusive_enable() local
32 struct clk_gate_exclusive *exgate = container_of(gate, in clk_gate_exclusive_enable()
33 struct clk_gate_exclusive, gate); in clk_gate_exclusive_enable()
34 u32 val = readl(gate->reg); in clk_gate_exclusive_enable()
62 struct clk_gate *gate; in imx_clk_hw_gate_exclusive() local
73 gate = &exgate->gate; in imx_clk_hw_gate_exclusive()
81 gate->reg = reg; in imx_clk_hw_gate_exclusive()
82 gate->bit_idx = shift; in imx_clk_hw_gate_exclusive()
83 gate->lock = &imx_ccm_lock; in imx_clk_hw_gate_exclusive()
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-gate.c26 static inline u32 clk_gate_readl(struct clk_gate *gate) in clk_gate_readl() argument
28 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_readl()
29 return ioread32be(gate->reg); in clk_gate_readl()
31 return readl(gate->reg); in clk_gate_readl()
34 static inline void clk_gate_writel(struct clk_gate *gate, u32 val) in clk_gate_writel() argument
36 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_writel()
37 iowrite32be(val, gate->reg); in clk_gate_writel()
39 writel(val, gate->reg); in clk_gate_writel()
57 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_endisable() local
58 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_gate_endisable()
[all …]
Dclk-ast2600.c233 static u32 get_reset_reg(struct aspeed_clk_gate *gate) in get_reset_reg() argument
235 if (gate->reset_idx < 32) in get_reset_reg()
241 static u32 get_clock_reg(struct aspeed_clk_gate *gate) in get_clock_reg() argument
243 if (gate->clock_idx < 32) in get_clock_reg()
251 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_g6_clk_is_enabled() local
252 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_is_enabled()
253 u32 rst = get_bit(gate->reset_idx); in aspeed_g6_clk_is_enabled()
263 if (gate->reset_idx >= 0) { in aspeed_g6_clk_is_enabled()
264 regmap_read(gate->map, get_reset_reg(gate), &reg); in aspeed_g6_clk_is_enabled()
270 regmap_read(gate->map, get_clock_reg(gate), &reg); in aspeed_g6_clk_is_enabled()
[all …]
Dclk-aspeed.c186 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_is_enabled() local
187 u32 clk = BIT(gate->clock_idx); in aspeed_clk_is_enabled()
188 u32 rst = BIT(gate->reset_idx); in aspeed_clk_is_enabled()
189 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_clk_is_enabled()
198 if (gate->reset_idx >= 0) { in aspeed_clk_is_enabled()
199 regmap_read(gate->map, ASPEED_RESET_CTRL, &reg); in aspeed_clk_is_enabled()
204 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg); in aspeed_clk_is_enabled()
211 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_enable() local
213 u32 clk = BIT(gate->clock_idx); in aspeed_clk_enable()
214 u32 rst = BIT(gate->reset_idx); in aspeed_clk_enable()
[all …]
/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_power.c75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
94 gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
96 sm750_set_current_gate(gate); in sm750_enable_2d_engine()
101 u32 gate; in sm750_enable_dma() local
104 gate = peek32(CURRENT_GATE); in sm750_enable_dma()
[all …]
/kernel/linux/linux-5.10/arch/ia64/kernel/
DMakefile.gate4 targets += gate.so gate.lds gate.o gate-dummy.o
6 obj-y += gate-syms.o
13 GATECFLAGS_gate.so = -shared -s -Wl,-soname=linux-gate.so.1 \
15 $(obj)/gate.so: $(obj)/gate.lds $(obj)/gate.o FORCE
16 $(call if_changed,gate)
19 $(obj)/gate-dummy.o: $(obj)/gate.lds $(obj)/gate.o FORCE
20 $(call if_changed,gate)
23 $(obj)/gate-syms.o: $(obj)/gate-dummy.o FORCE
29 $(obj)/gate-data.o: $(obj)/gate.so
/kernel/linux/linux-5.10/drivers/clk/uniphier/
Dclk-uniphier-gate.c25 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_endisable() local
27 return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), in uniphier_clk_gate_endisable()
28 enable ? BIT(gate->bit) : 0); in uniphier_clk_gate_endisable()
44 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_is_enabled() local
47 if (regmap_read(gate->regmap, gate->reg, &val) < 0) in uniphier_clk_gate_is_enabled()
50 return !!(val & BIT(gate->bit)); in uniphier_clk_gate_is_enabled()
64 struct uniphier_clk_gate *gate; in uniphier_clk_register_gate() local
68 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); in uniphier_clk_register_gate()
69 if (!gate) in uniphier_clk_register_gate()
78 gate->regmap = regmap; in uniphier_clk_register_gate()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Dgate.txt1 Binding for Texas Instruments gate clock.
6 quite much similar to the basic gate-clock [2], however,
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
23 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
26 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
28 "ti,composite-gate-clock" - composite gate clock, to be part of composite
[all …]
/kernel/linux/linux-5.10/drivers/clk/ingenic/
Djz4770-cgu.c174 .gate = { CGU_REG_CLKGR1, 7 },
191 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
209 .gate = { CGU_REG_MSC0CDR, 31 },
216 .gate = { CGU_REG_MSC1CDR, 31 },
223 .gate = { CGU_REG_MSC2CDR, 31 },
230 .gate = { CGU_REG_CLKGR0, 26 },
237 .gate = { CGU_REG_CLKGR0, 24 },
244 .gate = { CGU_REG_CLKGR1, 9 },
251 .gate = { CGU_REG_CLKGR0, 1 },
258 .gate = { CGU_REG_CLKGR0, 28 },
[all …]
Djz4780-cgu.c394 .gate = { CGU_REG_CLKGR1, 2 },
436 .gate = { CGU_REG_CLKGR0, 3 },
443 .gate = { CGU_REG_CLKGR0, 11 },
450 .gate = { CGU_REG_CLKGR0, 12 },
459 .gate = { CGU_REG_CLKGR0, 24 },
494 .gate = { CGU_REG_CLKGR1, 3 },
503 .gate = { CGU_REG_CLKGR1, 4 },
512 .gate = { CGU_REG_CLKGR1, 9 },
521 .gate = { CGU_REG_CLKGR0, 1 },
541 .gate = { CGU_REG_CLKGR0, 0 },
[all …]
Dx1830-cgu.c230 .gate = { CGU_REG_CLKGR1, 15 },
262 .gate = { CGU_REG_CLKGR1, 14 },
270 .gate = { CGU_REG_CLKGR0, 31 },
279 .gate = { CGU_REG_CLKGR1, 4 },
288 .gate = { CGU_REG_CLKGR1, 9 },
302 .gate = { CGU_REG_CLKGR0, 4 },
309 .gate = { CGU_REG_CLKGR0, 5 },
342 .gate = { CGU_REG_CLKGR0, 29 },
350 .gate = { CGU_REG_CLKGR0, 0 },
356 .gate = { CGU_REG_CLKGR0, 1 },
[all …]
Djz4740-cgu.c146 .gate = { CGU_REG_CLKGR, 10 },
160 .gate = { CGU_REG_CLKGR, 6 },
168 .gate = { CGU_REG_CLKGR, 4 },
175 .gate = { CGU_REG_CLKGR, 7 },
182 .gate = { CGU_REG_CLKGR, 14 },
190 .gate = { CGU_REG_SCR, 6, true },
198 .gate = { CGU_REG_CLKGR, 0 },
204 .gate = { CGU_REG_CLKGR, 15 },
210 .gate = { CGU_REG_CLKGR, 12 },
216 .gate = { CGU_REG_CLKGR, 13 },
[all …]
Dx1000-cgu.c256 .gate = { CGU_REG_CLKGR, 30 },
288 .gate = { CGU_REG_CLKGR, 28 },
296 .gate = { CGU_REG_CLKGR, 31 },
304 .gate = { CGU_REG_CLKGR, 25 },
312 .gate = { CGU_REG_CLKGR, 23 },
325 .gate = { CGU_REG_CLKGR, 4 },
332 .gate = { CGU_REG_CLKGR, 5 },
341 .gate = { CGU_REG_CLKGR, 3 },
373 .gate = { CGU_REG_CLKGR, 27 },
381 .gate = { CGU_REG_CLKGR, 0 },
[all …]
Djz4725b-cgu.c131 .gate = { CGU_REG_CLKGR, 13 },
138 .gate = { CGU_REG_CLKGR, 9 },
153 .gate = { CGU_REG_CLKGR, 4 },
174 .gate = { CGU_REG_CLKGR, 0 },
180 .gate = { CGU_REG_CLKGR, 12 },
186 .gate = { CGU_REG_CLKGR, 7 },
192 .gate = { CGU_REG_CLKGR, 3 },
198 .gate = { CGU_REG_CLKGR, 5 },
204 .gate = { CGU_REG_CLKGR, 6 },
210 .gate = { CGU_REG_CLKGR, 16 },
[all …]
/kernel/linux/linux-5.10/drivers/clk/zynqmp/
Dclk-gate-zynqmp.c36 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_enable() local
38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable()
56 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_disable() local
58 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable()
76 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_is_enabled() local
78 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled()
112 struct zynqmp_clk_gate *gate; in zynqmp_clk_register_gate() local
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in zynqmp_clk_register_gate()
119 if (!gate) in zynqmp_clk_register_gate()
129 gate->flags = nodes->type_flag; in zynqmp_clk_register_gate()
[all …]
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-kona.c358 __is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __is_clk_gate_enabled() argument
364 if (!gate_exists(gate)) in __is_clk_gate_enabled()
367 bit_mask = 1 << gate->status_bit; in __is_clk_gate_enabled()
368 reg_val = __ccu_read(ccu, gate->offset); in __is_clk_gate_enabled()
375 is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in is_clk_gate_enabled() argument
381 if (!gate_exists(gate)) in is_clk_gate_enabled()
385 ret = __is_clk_gate_enabled(ccu, gate); in is_clk_gate_enabled()
396 __gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __gate_commit() argument
402 BUG_ON(!gate_exists(gate)); in __gate_commit()
403 if (!gate_is_sw_controllable(gate)) in __gate_commit()
[all …]
Dclk-bcm281xx.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
42 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
51 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
84 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
103 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
115 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
127 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
139 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
151 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
162 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
[all …]
Dclk-bcm21664.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
41 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
66 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
78 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
90 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
102 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
115 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
120 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
125 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
130 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
[all …]
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mtk.c117 const struct mtk_gate *gate = &clks[i]; in mtk_clk_register_gates_with_dev() local
119 if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) in mtk_clk_register_gates_with_dev()
122 clk = mtk_clk_register_gate(gate->name, gate->parent_name, in mtk_clk_register_gates_with_dev()
124 gate->regs->set_ofs, in mtk_clk_register_gates_with_dev()
125 gate->regs->clr_ofs, in mtk_clk_register_gates_with_dev()
126 gate->regs->sta_ofs, in mtk_clk_register_gates_with_dev()
127 gate->shift, gate->ops, gate->flags, dev); in mtk_clk_register_gates_with_dev()
131 gate->name, PTR_ERR(clk)); in mtk_clk_register_gates_with_dev()
135 clk_data->clks[gate->id] = clk; in mtk_clk_register_gates_with_dev()
154 struct clk_gate *gate = NULL; in mtk_clk_register_composite() local
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-a10-mod1.c25 struct clk_gate *gate; in sun4i_mod1_clk_setup() local
39 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun4i_mod1_clk_setup()
40 if (!gate) in sun4i_mod1_clk_setup()
46 gate->reg = reg; in sun4i_mod1_clk_setup()
47 gate->bit_idx = SUN4I_MOD1_ENABLE; in sun4i_mod1_clk_setup()
48 gate->lock = &mod1_lock; in sun4i_mod1_clk_setup()
57 &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT); in sun4i_mod1_clk_setup()
66 kfree(gate); in sun4i_mod1_clk_setup()
/kernel/linux/linux-5.10/arch/x86/include/asm/
Ddesc.h79 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, in pack_gate() argument
82 gate->offset_low = (u16) func; in pack_gate()
83 gate->bits.p = 1; in pack_gate()
84 gate->bits.dpl = dpl; in pack_gate()
85 gate->bits.zero = 0; in pack_gate()
86 gate->bits.type = type; in pack_gate()
87 gate->offset_middle = (u16) (func >> 16); in pack_gate()
89 gate->segment = __KERNEL_CS; in pack_gate()
90 gate->bits.ist = ist; in pack_gate()
91 gate->reserved = 0; in pack_gate()
[all …]
/kernel/linux/linux-5.10/drivers/clk/actions/
Dowl-gate.c36 struct owl_gate *gate = hw_to_owl_gate(hw); in owl_gate_disable() local
37 struct owl_clk_common *common = &gate->common; in owl_gate_disable()
39 owl_gate_set(common, &gate->gate_hw, false); in owl_gate_disable()
44 struct owl_gate *gate = hw_to_owl_gate(hw); in owl_gate_enable() local
45 struct owl_clk_common *common = &gate->common; in owl_gate_enable()
47 owl_gate_set(common, &gate->gate_hw, true); in owl_gate_enable()
67 struct owl_gate *gate = hw_to_owl_gate(hw); in owl_gate_is_enabled() local
68 struct owl_clk_common *common = &gate->common; in owl_gate_is_enabled()
70 return owl_gate_clk_is_enabled(common, &gate->gate_hw); in owl_gate_is_enabled()

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