| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | base.c | 31 struct nvkm_gr *gr = device->gr; in nvkm_gr_ctxsw_inst() local
32 if (gr && gr->func->ctxsw.inst) in nvkm_gr_ctxsw_inst()
33 return gr->func->ctxsw.inst(gr); in nvkm_gr_ctxsw_inst()
40 struct nvkm_gr *gr = device->gr; in nvkm_gr_ctxsw_resume() local
41 if (gr && gr->func->ctxsw.resume) in nvkm_gr_ctxsw_resume()
42 return gr->func->ctxsw.resume(gr); in nvkm_gr_ctxsw_resume()
49 struct nvkm_gr *gr = device->gr; in nvkm_gr_ctxsw_pause() local
50 if (gr && gr->func->ctxsw.pause) in nvkm_gr_ctxsw_pause()
51 return gr->func->ctxsw.pause(gr); in nvkm_gr_ctxsw_pause()
58 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_chsw_load() local
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| D | gf100.c | 49 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) in gf100_gr_zbc_clear_color() argument
51 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_zbc_clear_color()
52 if (gr->zbc_color[zbc].format) { in gf100_gr_zbc_clear_color()
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
64 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, in gf100_gr_zbc_color_get() argument
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_color_get()
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| D | Kbuild | 2 nvkm-y += nvkm/engine/gr/base.o
3 nvkm-y += nvkm/engine/gr/nv04.o
4 nvkm-y += nvkm/engine/gr/nv10.o
5 nvkm-y += nvkm/engine/gr/nv15.o
6 nvkm-y += nvkm/engine/gr/nv17.o
7 nvkm-y += nvkm/engine/gr/nv20.o
8 nvkm-y += nvkm/engine/gr/nv25.o
9 nvkm-y += nvkm/engine/gr/nv2a.o
10 nvkm-y += nvkm/engine/gr/nv30.o
11 nvkm-y += nvkm/engine/gr/nv34.o
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| D | ctxgf100.c | 1012 struct nvkm_device *device = info->gr->base.engine.subdev.device; in gf100_grctx_mmio_item()
1033 gf100_grctx_generate_r419cb8(struct gf100_gr *gr) in gf100_grctx_generate_r419cb8() argument
1035 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_grctx_generate_r419cb8()
1042 const struct gf100_grctx_func *grctx = info->gr->func->grctx; in gf100_grctx_generate_bundle()
1054 const struct gf100_grctx_func *grctx = info->gr->func->grctx; in gf100_grctx_generate_pagepool()
1066 struct gf100_gr *gr = info->gr; in gf100_grctx_generate_attrib() local
1067 const struct gf100_grctx_func *grctx = gr->func->grctx; in gf100_grctx_generate_attrib()
1071 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gf100_grctx_generate_attrib()
1079 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_attrib()
1080 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_grctx_generate_attrib()
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| D | ctxgm20b.c | 25 gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) in gm20b_grctx_generate_main() argument
27 struct nvkm_device *device = gr->base.engine.subdev.device; in gm20b_grctx_generate_main()
28 const struct gf100_grctx_func *grctx = gr->func->grctx; in gm20b_grctx_generate_main()
32 gf100_gr_mmio(gr, gr->sw_ctx); in gm20b_grctx_generate_main()
34 gf100_gr_wait_idle(gr); in gm20b_grctx_generate_main()
40 grctx->unkn(gr); in gm20b_grctx_generate_main()
42 gf100_grctx_generate_floorsweep(gr); in gm20b_grctx_generate_main()
47 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm20b_grctx_generate_main()
51 for (tmp = 0, i = 0; i < gr->gpc_nr; i++) in gm20b_grctx_generate_main()
52 tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); in gm20b_grctx_generate_main()
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| D | gk20a.c | 37 gk20a_gr_av_to_init(struct gf100_gr *gr, const char *path, const char *name, in gk20a_gr_av_to_init() argument
40 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gk20a_gr_av_to_init()
87 gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *path, const char *name, in gk20a_gr_aiv_to_init() argument
90 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gk20a_gr_aiv_to_init()
130 gk20a_gr_av_to_method(struct gf100_gr *gr, const char *path, const char *name, in gk20a_gr_av_to_method() argument
133 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gk20a_gr_av_to_method()
191 gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) in gk20a_gr_wait_mem_scrubbing() argument
193 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gk20a_gr_wait_mem_scrubbing()
216 gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr) in gk20a_gr_set_hww_esr_report_mask() argument
218 struct nvkm_device *device = gr->base.engine.subdev.device; in gk20a_gr_set_hww_esr_report_mask()
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| D | gm200.c | 36 gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) in gm200_gr_nofw() argument
38 nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n"); in gm200_gr_nofw()
93 gm200_gr_rops(struct gf100_gr *gr) in gm200_gr_rops() argument
95 return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); in gm200_gr_rops()
99 gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr) in gm200_gr_init_ds_hww_esr_2() argument
101 struct nvkm_device *device = gr->base.engine.subdev.device; in gm200_gr_init_ds_hww_esr_2()
107 gm200_gr_init_num_active_ltcs(struct gf100_gr *gr) in gm200_gr_init_num_active_ltcs() argument
109 struct nvkm_device *device = gr->base.engine.subdev.device; in gm200_gr_init_num_active_ltcs()
115 gm200_gr_init_gpc_mmu(struct gf100_gr *gr) in gm200_gr_init_gpc_mmu() argument
117 struct nvkm_device *device = gr->base.engine.subdev.device; in gm200_gr_init_gpc_mmu()
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| D | ctxgm200.c | 31 gm200_grctx_generate_r419a3c(struct gf100_gr *gr) in gm200_grctx_generate_r419a3c() argument
33 struct nvkm_device *device = gr->base.engine.subdev.device; in gm200_grctx_generate_r419a3c()
38 gm200_grctx_generate_r418e94(struct gf100_gr *gr) in gm200_grctx_generate_r418e94() argument
40 struct nvkm_device *device = gr->base.engine.subdev.device; in gm200_grctx_generate_r418e94()
46 gm200_grctx_generate_smid_config(struct gf100_gr *gr) in gm200_grctx_generate_smid_config() argument
48 struct nvkm_device *device = gr->base.engine.subdev.device; in gm200_grctx_generate_smid_config()
49 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gm200_grctx_generate_smid_config()
54 for (sm = 0; sm < gr->sm_nr; sm++) { in gm200_grctx_generate_smid_config()
55 const u8 gpc = gr->sm[sm].gpc; in gm200_grctx_generate_smid_config()
56 const u8 tpc = gr->sm[sm].tpc; in gm200_grctx_generate_smid_config()
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| D | ctxgv100.c | 64 struct gf100_gr *gr = info->gr; in gv100_grctx_generate_attrib() local
65 const struct gf100_grctx_func *grctx = gr->func->grctx; in gv100_grctx_generate_attrib()
70 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gv100_grctx_generate_attrib()
75 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gv100_grctx_generate_attrib()
76 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gv100_grctx_generate_attrib()
88 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_grctx_generate_attrib()
89 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gv100_grctx_generate_attrib()
90 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
91 const u32 bs = attrib * gr->ppc_tpc_max; in gv100_grctx_generate_attrib()
92 const u32 gs = gfxp * gr->ppc_tpc_max; in gv100_grctx_generate_attrib()
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| D | ctxgk20a.c | 28 gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) in gk20a_grctx_generate_main() argument
30 struct nvkm_device *device = gr->base.engine.subdev.device; in gk20a_grctx_generate_main()
31 const struct gf100_grctx_func *grctx = gr->func->grctx; in gk20a_grctx_generate_main()
35 gf100_gr_mmio(gr, gr->sw_ctx); in gk20a_grctx_generate_main()
37 gf100_gr_wait_idle(gr); in gk20a_grctx_generate_main()
43 grctx->unkn(gr); in gk20a_grctx_generate_main()
45 gf100_grctx_generate_floorsweep(gr); in gk20a_grctx_generate_main()
50 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk20a_grctx_generate_main()
54 gf100_gr_wait_idle(gr); in gk20a_grctx_generate_main()
57 gf100_gr_wait_idle(gr); in gk20a_grctx_generate_main()
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| D | nv10.c | 401 struct nv10_gr *gr; member
414 #define PIPE_SAVE(gr, state, addr) \ argument
422 #define PIPE_RESTORE(gr, state, addr) \ argument
434 struct nvkm_gr *gr = &chan->gr->base; in nv17_gr_mthd_lma_window() local
445 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
452 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
462 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
485 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
500 nv04_gr_idle(gr); in nv17_gr_mthd_lma_window()
507 struct nvkm_gr *gr = &chan->gr->base; in nv17_gr_mthd_lma_enable() local
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| D | tu102.c | 28 tu102_gr_init_fecs_exceptions(struct gf100_gr *gr) in tu102_gr_init_fecs_exceptions() argument
30 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002); in tu102_gr_init_fecs_exceptions()
34 tu102_gr_init_fs(struct gf100_gr *gr) in tu102_gr_init_fs() argument
36 struct nvkm_device *device = gr->base.engine.subdev.device; in tu102_gr_init_fs()
39 gp100_grctx_generate_smid_config(gr); in tu102_gr_init_fs()
40 gk104_grctx_generate_gpc_tpc_nr(gr); in tu102_gr_init_fs()
42 for (sm = 0; sm < gr->sm_nr; sm++) { in tu102_gr_init_fs()
43 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + in tu102_gr_init_fs()
44 gr->sm[sm].tpc * 4), sm); in tu102_gr_init_fs()
47 gm200_grctx_generate_dist_skip_table(gr); in tu102_gr_init_fs()
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| D | gp100.c | 33 gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) in gp100_gr_zbc_clear_color() argument
35 struct nvkm_device *device = gr->base.engine.subdev.device; in gp100_gr_zbc_clear_color()
39 if (gr->zbc_color[zbc].format) { in gp100_gr_zbc_clear_color()
40 nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]); in gp100_gr_zbc_clear_color()
41 nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]); in gp100_gr_zbc_clear_color()
42 nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]); in gp100_gr_zbc_clear_color()
43 nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]); in gp100_gr_zbc_clear_color()
48 gr->zbc_color[zbc].format << ((znum % 4) * 7)); in gp100_gr_zbc_clear_color()
52 gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) in gp100_gr_zbc_clear_depth() argument
54 struct nvkm_device *device = gr->base.engine.subdev.device; in gp100_gr_zbc_clear_depth()
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| D | ctxgf117.c | 188 gf117_grctx_generate_dist_skip_table(struct gf100_gr *gr) in gf117_grctx_generate_dist_skip_table() argument
190 struct nvkm_device *device = gr->base.engine.subdev.device; in gf117_grctx_generate_dist_skip_table()
198 gf117_grctx_generate_rop_mapping(struct gf100_gr *gr) in gf117_grctx_generate_rop_mapping() argument
200 struct nvkm_device *device = gr->base.engine.subdev.device; in gf117_grctx_generate_rop_mapping()
207 data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5); in gf117_grctx_generate_rop_mapping()
211 ntpcv = gr->tpc_total; in gf117_grctx_generate_rop_mapping()
224 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
225 gr->screen_tile_row_offset); in gf117_grctx_generate_rop_mapping()
230 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
231 gr->screen_tile_row_offset | data2[0]); in gf117_grctx_generate_rop_mapping()
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| D | ctxgp100.c | 35 const struct gf100_grctx_func *grctx = info->gr->func->grctx; in gp100_grctx_generate_pagepool()
47 struct gf100_gr *gr = info->gr; in gp100_grctx_generate_attrib() local
48 const struct gf100_grctx_func *grctx = gr->func->grctx; in gp100_grctx_generate_attrib()
53 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp100_grctx_generate_attrib()
58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp100_grctx_generate_attrib()
59 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp100_grctx_generate_attrib()
72 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp100_grctx_generate_attrib()
73 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp100_grctx_generate_attrib()
74 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
75 const u32 bs = attrib * gr->ppc_tpc_max; in gp100_grctx_generate_attrib()
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| D | gp102.c | 30 gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc) in gp102_gr_zbc_clear_stencil() argument
32 struct nvkm_device *device = gr->base.engine.subdev.device; in gp102_gr_zbc_clear_stencil()
36 if (gr->zbc_stencil[zbc].format) in gp102_gr_zbc_clear_stencil()
37 nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds); in gp102_gr_zbc_clear_stencil()
40 gr->zbc_stencil[zbc].format << ((znum % 4) * 7)); in gp102_gr_zbc_clear_stencil()
44 gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format, in gp102_gr_zbc_stencil_get() argument
47 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gp102_gr_zbc_stencil_get()
51 if (gr->zbc_stencil[i].format) { in gp102_gr_zbc_stencil_get()
52 if (gr->zbc_stencil[i].format != format) in gp102_gr_zbc_stencil_get()
54 if (gr->zbc_stencil[i].ds != ds) in gp102_gr_zbc_stencil_get()
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| D | ctxgp102.c | 33 gp102_grctx_generate_r408840(struct gf100_gr *gr) in gp102_grctx_generate_r408840() argument
35 struct nvkm_device *device = gr->base.engine.subdev.device; in gp102_grctx_generate_r408840()
42 struct gf100_gr *gr = info->gr; in gp102_grctx_generate_attrib() local
43 const struct gf100_grctx_func *grctx = gr->func->grctx; in gp102_grctx_generate_attrib()
49 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp102_grctx_generate_attrib()
54 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp102_grctx_generate_attrib()
55 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp102_grctx_generate_attrib()
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_grctx_generate_attrib()
69 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp102_grctx_generate_attrib()
70 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
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| D | ctxgk104.c | 849 gk104_grctx_generate_r418800(struct gf100_gr *gr) in gk104_grctx_generate_r418800() argument
851 struct nvkm_device *device = gr->base.engine.subdev.device; in gk104_grctx_generate_r418800()
866 struct nvkm_device *device = info->gr->base.engine.subdev.device; in gk104_grctx_generate_patch_ltc()
877 const struct gf100_grctx_func *grctx = info->gr->func->grctx; in gk104_grctx_generate_bundle()
893 const struct gf100_grctx_func *grctx = info->gr->func->grctx; in gk104_grctx_generate_pagepool()
904 gk104_grctx_generate_unkn(struct gf100_gr *gr) in gk104_grctx_generate_unkn() argument
906 struct nvkm_device *device = gr->base.engine.subdev.device; in gk104_grctx_generate_unkn()
916 gk104_grctx_generate_r419f78(struct gf100_gr *gr) in gk104_grctx_generate_r419f78() argument
918 struct nvkm_device *device = gr->base.engine.subdev.device; in gk104_grctx_generate_r419f78()
923 gk104_grctx_generate_gpc_tpc_nr(struct gf100_gr *gr) in gk104_grctx_generate_gpc_tpc_nr() argument
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| D | nv40.c | 34 nv40_gr_units(struct nvkm_gr *gr) in nv40_gr_units() argument
36 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv40_gr_units()
78 struct nv40_gr *gr = chan->gr; in nv40_gr_chan_bind() local
79 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in nv40_gr_chan_bind()
84 nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); in nv40_gr_chan_bind()
95 struct nv40_gr *gr = chan->gr; in nv40_gr_chan_fini() local
96 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in nv40_gr_chan_fini()
134 spin_lock_irqsave(&chan->gr->base.engine.lock, flags); in nv40_gr_chan_dtor()
136 spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); in nv40_gr_chan_dtor()
151 struct nv40_gr *gr = nv40_gr(base); in nv40_gr_chan_new() local
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| D | ctxgm107.c | 869 gm107_grctx_generate_r419e00(struct gf100_gr *gr) in gm107_grctx_generate_r419e00() argument
871 struct nvkm_device *device = gr->base.engine.subdev.device; in gm107_grctx_generate_r419e00()
881 const struct gf100_grctx_func *grctx = info->gr->func->grctx; in gm107_grctx_generate_bundle()
897 const struct gf100_grctx_func *grctx = info->gr->func->grctx; in gm107_grctx_generate_pagepool()
911 struct gf100_gr *gr = info->gr; in gm107_grctx_generate_attrib() local
912 const struct gf100_grctx_func *grctx = gr->func->grctx; in gm107_grctx_generate_attrib()
917 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gm107_grctx_generate_attrib()
920 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gm107_grctx_generate_attrib()
929 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm107_grctx_generate_attrib()
930 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gm107_grctx_generate_attrib()
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| /kernel/linux/linux-5.10/arch/parisc/kernel/ |
| D | kgdb.c | 64 struct parisc_gdb_regs *gr = (struct parisc_gdb_regs *)gdb_regs; in pt_regs_to_gdb_regs() local
66 memset(gr, 0, sizeof(struct parisc_gdb_regs)); in pt_regs_to_gdb_regs()
68 memcpy(gr->gpr, regs->gr, sizeof(gr->gpr)); in pt_regs_to_gdb_regs()
69 memcpy(gr->fr, regs->fr, sizeof(gr->fr)); in pt_regs_to_gdb_regs()
71 gr->sr0 = regs->sr[0]; in pt_regs_to_gdb_regs()
72 gr->sr1 = regs->sr[1]; in pt_regs_to_gdb_regs()
73 gr->sr2 = regs->sr[2]; in pt_regs_to_gdb_regs()
74 gr->sr3 = regs->sr[3]; in pt_regs_to_gdb_regs()
75 gr->sr4 = regs->sr[4]; in pt_regs_to_gdb_regs()
76 gr->sr5 = regs->sr[5]; in pt_regs_to_gdb_regs()
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| D | ptrace.c | 160 task_regs(child)->gr[0] &= ~USER_PSW_BITS; in arch_ptrace()
161 task_regs(child)->gr[0] |= data; in arch_ptrace()
325 regs->gr[28] = -ENOSYS; in do_syscall_trace_enter()
338 regs->gr[20] = -1UL; in do_syscall_trace_enter()
349 trace_sys_enter(regs, regs->gr[20]); in do_syscall_trace_enter()
354 audit_syscall_entry(regs->gr[20], regs->gr[26], regs->gr[25], in do_syscall_trace_enter()
355 regs->gr[24], regs->gr[23]); in do_syscall_trace_enter()
358 audit_syscall_entry(regs->gr[20] & 0xffffffff, in do_syscall_trace_enter()
359 regs->gr[26] & 0xffffffff, in do_syscall_trace_enter()
360 regs->gr[25] & 0xffffffff, in do_syscall_trace_enter()
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| D | asm-offsets.c | 54 DEFINE(TASK_PT_PSW, offsetof(struct task_struct, thread.regs.gr[ 0])); in main()
55 DEFINE(TASK_PT_GR1, offsetof(struct task_struct, thread.regs.gr[ 1])); in main()
56 DEFINE(TASK_PT_GR2, offsetof(struct task_struct, thread.regs.gr[ 2])); in main()
57 DEFINE(TASK_PT_GR3, offsetof(struct task_struct, thread.regs.gr[ 3])); in main()
58 DEFINE(TASK_PT_GR4, offsetof(struct task_struct, thread.regs.gr[ 4])); in main()
59 DEFINE(TASK_PT_GR5, offsetof(struct task_struct, thread.regs.gr[ 5])); in main()
60 DEFINE(TASK_PT_GR6, offsetof(struct task_struct, thread.regs.gr[ 6])); in main()
61 DEFINE(TASK_PT_GR7, offsetof(struct task_struct, thread.regs.gr[ 7])); in main()
62 DEFINE(TASK_PT_GR8, offsetof(struct task_struct, thread.regs.gr[ 8])); in main()
63 DEFINE(TASK_PT_GR9, offsetof(struct task_struct, thread.regs.gr[ 9])); in main()
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| D | signal.c | 75 err |= __copy_from_user(regs->gr, sc->sc_gr, sizeof(regs->gr)); in restore_sigcontext()
82 DBG(2,"restore_sigcontext: r28 is %ld\n", regs->gr[28]); in restore_sigcontext()
91 unsigned long usp = (regs->gr[30] & ~(0x01UL)); in sys_rt_sigreturn()
157 regs->gr[31] = regs->iaoq[0]; in sys_rt_sigreturn()
204 err |= __put_user(regs->gr[31], &sc->sc_iaoq[0]); in setup_sigcontext()
205 err |= __put_user(regs->gr[31]+4, &sc->sc_iaoq[1]); in setup_sigcontext()
209 regs->gr[31], regs->gr[31]+4); in setup_sigcontext()
218 err |= __copy_to_user(sc->sc_gr, regs->gr, sizeof(regs->gr)); in setup_sigcontext()
221 DBG(1,"setup_sigcontext: r28 is %ld\n", regs->gr[28]); in setup_sigcontext()
239 usp = (regs->gr[30] & ~(0x01UL)); in setup_rt_frame()
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| /kernel/linux/linux-5.10/arch/parisc/include/asm/ |
| D | syscall.h | 17 return regs->gr[20]; in syscall_get_nr()
24 args[5] = regs->gr[21]; in syscall_get_arguments()
25 args[4] = regs->gr[22]; in syscall_get_arguments()
26 args[3] = regs->gr[23]; in syscall_get_arguments()
27 args[2] = regs->gr[24]; in syscall_get_arguments()
28 args[1] = regs->gr[25]; in syscall_get_arguments()
29 args[0] = regs->gr[26]; in syscall_get_arguments()
35 unsigned long error = regs->gr[28]; in syscall_get_error()
42 return regs->gr[28]; in syscall_get_return_value()
49 regs->gr[28] = error ? error : val; in syscall_set_return_value()
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