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Searched refs:gvt (Results 1 – 25 of 37) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
Dgvt.c49 static struct intel_vgpu_type *intel_gvt_find_vgpu_type(struct intel_gvt *gvt, in intel_gvt_find_vgpu_type() argument
53 dev_driver_string(&gvt->gt->i915->drm.pdev->dev); in intel_gvt_find_vgpu_type()
57 for (i = 0; i < gvt->num_types; i++) { in intel_gvt_find_vgpu_type()
58 struct intel_vgpu_type *t = &gvt->types[i]; in intel_gvt_find_vgpu_type()
72 void *gvt = kdev_to_i915(dev)->gvt; in available_instances_show() local
74 type = intel_gvt_find_vgpu_type(gvt, kobject_name(kobj)); in available_instances_show()
93 void *gvt = kdev_to_i915(dev)->gvt; in description_show() local
95 type = intel_gvt_find_vgpu_type(gvt, kobject_name(kobj)); in description_show()
129 static int intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt) in intel_gvt_init_vgpu_type_groups() argument
135 for (i = 0; i < gvt->num_types; i++) { in intel_gvt_init_vgpu_type_groups()
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Dvgpu.c40 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in populate_pvinfo_page()
107 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) in intel_gvt_init_vgpu_types() argument
125 low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; in intel_gvt_init_vgpu_types()
126 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; in intel_gvt_init_vgpu_types()
129 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type), in intel_gvt_init_vgpu_types()
131 if (!gvt->types) in intel_gvt_init_vgpu_types()
139 gvt->types[i].low_gm_size = vgpu_types[i].low_mm; in intel_gvt_init_vgpu_types()
140 gvt->types[i].high_gm_size = vgpu_types[i].high_mm; in intel_gvt_init_vgpu_types()
141 gvt->types[i].fence = vgpu_types[i].fence; in intel_gvt_init_vgpu_types()
147 gvt->types[i].weight = vgpu_types[i].weight; in intel_gvt_init_vgpu_types()
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Dsched_policy.c42 for_each_engine(engine, vgpu->gvt->gt, i) { in vgpu_has_pending_workload()
68 struct intel_gvt *gvt; member
80 if (!vgpu || vgpu == vgpu->gvt->idle_vgpu) in vgpu_update_timeslice()
132 static void try_to_schedule_next_vgpu(struct intel_gvt *gvt) in try_to_schedule_next_vgpu() argument
134 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in try_to_schedule_next_vgpu()
155 for_each_engine(engine, gvt->gt, i) { in try_to_schedule_next_vgpu()
172 for_each_engine(engine, gvt->gt, i) in try_to_schedule_next_vgpu()
213 struct intel_gvt *gvt = sched_data->gvt; in tbs_sched_func() local
214 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in tbs_sched_func()
233 scheduler->next_vgpu = gvt->idle_vgpu; in tbs_sched_func()
[all …]
Dgvt.h175 struct intel_gvt *gvt; member
336 return i915->gvt; in to_gvt()
349 static inline void intel_gvt_request_service(struct intel_gvt *gvt, in intel_gvt_request_service() argument
352 set_bit(service, (void *)&gvt->service_request); in intel_gvt_request_service()
353 wake_up(&gvt->service_thread_wq); in intel_gvt_request_service()
356 void intel_gvt_free_firmware(struct intel_gvt *gvt);
357 int intel_gvt_load_firmware(struct intel_gvt *gvt);
367 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) argument
370 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end argument
371 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start argument
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Daperture_gm.c43 struct intel_gvt *gvt = vgpu->gvt; in alloc_gm() local
44 struct intel_gt *gt = gvt->gt; in alloc_gm()
53 start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
54 end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
59 start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
60 end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
81 struct intel_gvt *gvt = vgpu->gvt; in alloc_vgpu_gm() local
82 struct intel_gt *gt = gvt->gt; in alloc_vgpu_gm()
109 struct intel_gvt *gvt = vgpu->gvt; in free_vgpu_gm() local
110 struct intel_gt *gt = gvt->gt; in free_vgpu_gm()
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Ddebugfs.c58 static inline int mmio_diff_handler(struct intel_gvt *gvt, in mmio_diff_handler() argument
65 preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset)); in mmio_diff_handler()
87 struct intel_gvt *gvt = vgpu->gvt; in vgpu_mmio_diff_show() local
97 mutex_lock(&gvt->lock); in vgpu_mmio_diff_show()
98 spin_lock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
100 mmio_hw_access_pre(gvt->gt); in vgpu_mmio_diff_show()
102 intel_gvt_for_each_tracked_mmio(gvt, mmio_diff_handler, &param); in vgpu_mmio_diff_show()
103 mmio_hw_access_post(gvt->gt); in vgpu_mmio_diff_show()
105 spin_unlock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
106 mutex_unlock(&gvt->lock); in vgpu_mmio_diff_show()
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Dmmio.c53 #define reg_is_mmio(gvt, reg) \ argument
54 (reg >= 0 && reg < gvt->device_info.mmio_size)
56 #define reg_is_gtt(gvt, reg) \ argument
57 (reg >= gvt->device_info.gtt_start_offset \
58 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
63 struct intel_gvt *gvt = NULL; in failsafe_emulate_mmio_rw() local
70 gvt = vgpu->gvt; in failsafe_emulate_mmio_rw()
73 if (reg_is_mmio(gvt, offset)) { in failsafe_emulate_mmio_rw()
80 } else if (reg_is_gtt(gvt, offset)) { in failsafe_emulate_mmio_rw()
81 offset -= gvt->device_info.gtt_start_offset; in failsafe_emulate_mmio_rw()
[all …]
Dfirmware.c69 static int mmio_snapshot_handler(struct intel_gvt *gvt, u32 offset, void *data) in mmio_snapshot_handler() argument
71 *(u32 *)(data + offset) = intel_uncore_read_notrace(gvt->gt->uncore, in mmio_snapshot_handler()
76 static int expose_firmware_sysfs(struct intel_gvt *gvt) in expose_firmware_sysfs() argument
78 struct intel_gvt_device_info *info = &gvt->device_info; in expose_firmware_sysfs()
79 struct pci_dev *pdev = gvt->gt->i915->drm.pdev; in expose_firmware_sysfs()
105 memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size); in expose_firmware_sysfs()
110 intel_gvt_for_each_tracked_mmio(gvt, mmio_snapshot_handler, p); in expose_firmware_sysfs()
112 memcpy(gvt->firmware.mmio, p, info->mmio_size); in expose_firmware_sysfs()
128 static void clean_firmware_sysfs(struct intel_gvt *gvt) in clean_firmware_sysfs() argument
130 struct pci_dev *pdev = gvt->gt->i915->drm.pdev; in clean_firmware_sysfs()
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Dgtt.c74 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_ggtt_gmadr_g2h()
92 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_ggtt_gmadr_h2g()
94 if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr), in intel_gvt_ggtt_gmadr_h2g()
98 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr)) in intel_gvt_ggtt_gmadr_h2g()
100 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt)); in intel_gvt_ggtt_gmadr_h2g()
103 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt)); in intel_gvt_ggtt_gmadr_h2g()
308 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; in gtt_get_entry64()
321 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index); in gtt_get_entry64()
333 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; in gtt_set_entry64()
346 write_pte64(vgpu->gvt->gt->ggtt, index, e->val64); in gtt_set_entry64()
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Dinterrupt.c147 struct intel_gvt *gvt, in regbase_to_irq_info() argument
150 struct intel_gvt_irq *irq = &gvt->irq; in regbase_to_irq_info()
178 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_imr_handler() local
179 struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_imr_handler()
208 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_master_irq_handler() local
209 struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_master_irq_handler()
247 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_ier_handler() local
248 struct drm_i915_private *i915 = gvt->gt->i915; in intel_vgpu_reg_ier_handler()
249 struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_ier_handler()
258 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); in intel_vgpu_reg_ier_handler()
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Dsched_policy.h41 int (*init)(struct intel_gvt *gvt);
42 void (*clean)(struct intel_gvt *gvt);
49 void intel_gvt_schedule(struct intel_gvt *gvt);
51 int intel_gvt_init_sched_policy(struct intel_gvt *gvt);
53 void intel_gvt_clean_sched_policy(struct intel_gvt *gvt);
63 void intel_gvt_kick_schedule(struct intel_gvt *gvt);
Dmmio.h73 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int reg);
74 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
75 bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
77 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
78 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
79 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
80 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
99 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
Dmmio_context.c162 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs() local
164 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
165 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
201 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit() local
203 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; in restore_context_mmio_for_inhibit()
217 for (mmio = gvt->engine_mmio_list.mmio; in restore_context_mmio_for_inhibit()
352 u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list; in handle_tlb_pending_event()
353 u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt; in handle_tlb_pending_event()
479 for (mmio = engine->i915->gvt->engine_mmio_list.mmio; in switch_mmio()
578 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) in intel_gvt_init_engine_mmio_context() argument
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Dscheduler.c83 struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915; in sr_oa_regs()
126 struct intel_gvt *gvt = vgpu->gvt; in populate_shadow_context() local
205 if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0) in populate_shadow_context()
272 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, in shadow_context_status_change() local
274 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in shadow_context_status_change()
504 struct intel_gvt *gvt = workload->vgpu->gvt; in prepare_shadow_batch_buffer() local
505 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; in prepare_shadow_batch_buffer()
800 pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine) in pick_next_workload() argument
802 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in pick_next_workload()
805 mutex_lock(&gvt->sched_lock); in pick_next_workload()
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Dcfg_space.c119 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_cfg_read()
125 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_read()
313 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_cfg_write()
320 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_write()
376 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_init_cfg_space() local
377 const struct intel_gvt_device_info *info = &gvt->device_info; in intel_vgpu_init_cfg_space()
381 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, in intel_vgpu_init_cfg_space()
396 gvt_aperture_pa_base(gvt), true); in intel_vgpu_init_cfg_space()
410 pci_resource_len(gvt->gt->i915->drm.pdev, 0); in intel_vgpu_init_cfg_space()
412 pci_resource_len(gvt->gt->i915->drm.pdev, 2); in intel_vgpu_init_cfg_space()
Ddisplay.c60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in edp_pipe_is_enabled()
72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in pipe_is_enabled()
172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_monitor_status_change()
521 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in setup_virtual_dp_monitor()
561 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) in intel_gvt_check_vblank_emulation() argument
563 struct intel_gvt_irq *irq = &gvt->irq; in intel_gvt_check_vblank_emulation()
568 mutex_lock(&gvt->lock); in intel_gvt_check_vblank_emulation()
569 for_each_active_vgpu(gvt, vgpu, id) { in intel_gvt_check_vblank_emulation()
587 mutex_unlock(&gvt->lock); in intel_gvt_check_vblank_emulation()
592 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_vblank_on_pipe()
[all …]
Dhandlers.c50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) in intel_gvt_get_device_type() argument
52 struct drm_i915_private *i915 = gvt->gt->i915; in intel_gvt_get_device_type()
68 bool intel_gvt_match_device(struct intel_gvt *gvt, in intel_gvt_match_device() argument
71 return intel_gvt_get_device_type(gvt) & device; in intel_gvt_match_device()
86 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, in find_mmio_info() argument
91 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { in find_mmio_info()
98 static int new_mmio_info(struct intel_gvt *gvt, in new_mmio_info() argument
106 if (!intel_gvt_match_device(gvt, device)) in new_mmio_info()
121 p = find_mmio_info(gvt, info->offset); in new_mmio_info()
138 gvt->mmio.mmio_attribute[info->offset / 4] = flags; in new_mmio_info()
[all …]
Dcmd_parser.h45 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
47 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
Dcmd_parser.c505 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
651 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode, in find_cmd_entry() argument
656 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { in find_cmd_entry()
665 get_cmd_info(struct intel_gvt *gvt, u32 cmd, in get_cmd_info() argument
674 return find_cmd_entry(gvt, opcode, engine); in get_cmd_info()
844 struct intel_gvt *gvt = s->vgpu->gvt; in force_nonpriv_reg_handler() local
860 if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) && in force_nonpriv_reg_handler()
930 struct intel_gvt *gvt = vgpu->gvt; in cmd_reg_handler() local
933 if (offset + 4 > gvt->device_info.mmio_size) { in cmd_reg_handler()
939 if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) { in cmd_reg_handler()
[all …]
DMakefile2 GVT_DIR := gvt
3 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
Dkvmgt.c154 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in gvt_unpin_guest_page()
224 struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev; in gvt_dma_map_page()
247 struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev; in gvt_dma_unmap_page()
697 void *gvt; in intel_vgpu_create() local
701 gvt = kdev_to_i915(pdev)->gvt; in intel_vgpu_create()
703 type = intel_gvt_ops->gvt_find_vgpu_type(gvt, kobject_name(kobj)); in intel_vgpu_create()
711 vgpu = intel_gvt_ops->vgpu_create(gvt, type); in intel_vgpu_create()
876 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in __intel_vgpu_release()
985 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, in intel_vgpu_aperture_rw()
1055 struct intel_gvt *gvt = vgpu->gvt; in gtt_entry() local
[all …]
Dmpt.h53 void *gvt, const void *ops) in intel_gvt_hypervisor_host_init() argument
58 return intel_gvt_host.mpt->host_init(dev, gvt, ops); in intel_gvt_hypervisor_host_init()
118 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset; in intel_gvt_hypervisor_inject_msi()
Dscheduler.h136 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
138 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
Dedid.c138 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in gmbus0_mmio_write()
279 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in gmbus3_mmio_write()
376 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_gmbus_read()
406 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_gmbus_write()
482 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_aux_ch_write()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
DMakefile277 include $(src)/gvt/Makefile
281 obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o
288 gvt/execlist.h \
289 gvt/fb_decoder.h \
290 gvt/gtt.h \
291 gvt/gvt.h \
292 gvt/interrupt.h \
293 gvt/mmio_context.h \
294 gvt/mpt.h \
295 gvt/scheduler.h

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