| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | rv730_dpm.c | 246 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
247 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ? in rv730_populate_smc_acpi_state()
249 table->ACPIState.levels[0].gen2XSP = in rv730_populate_smc_acpi_state()
253 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
254 table->ACPIState.levels[0].gen2PCIE = 0; in rv730_populate_smc_acpi_state()
296 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
297 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_smc_acpi_state()
298 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_smc_acpi_state()
299 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_smc_acpi_state()
300 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_smc_acpi_state()
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| D | rv740_dpm.c | 334 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
335 table->ACPIState.levels[0].gen2PCIE = in rv740_populate_smc_acpi_state()
338 table->ACPIState.levels[0].gen2XSP = in rv740_populate_smc_acpi_state()
342 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
343 table->ACPIState.levels[0].gen2PCIE = 0; in rv740_populate_smc_acpi_state()
373 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_smc_acpi_state()
374 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_smc_acpi_state()
375 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_smc_acpi_state()
376 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_smc_acpi_state()
377 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_smc_acpi_state()
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| D | cypress_dpm.c | 776 &smc_state->levels[0], in cypress_convert_power_state_to_smc()
783 &smc_state->levels[1], in cypress_convert_power_state_to_smc()
790 &smc_state->levels[2], in cypress_convert_power_state_to_smc()
795 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in cypress_convert_power_state_to_smc()
796 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in cypress_convert_power_state_to_smc()
797 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in cypress_convert_power_state_to_smc()
800 smc_state->levels[0].ACIndex = 2; in cypress_convert_power_state_to_smc()
801 smc_state->levels[1].ACIndex = 3; in cypress_convert_power_state_to_smc()
802 smc_state->levels[2].ACIndex = 4; in cypress_convert_power_state_to_smc()
804 smc_state->levels[0].ACIndex = 0; in cypress_convert_power_state_to_smc()
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| D | sumo_dpm.c | 347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
411 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
670 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
762 sumo_program_power_level(rdev, &new_ps->levels[i], i); in sumo_program_power_levels_0_to_n()
844 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
845 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
862 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
863 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_after_set_eng_clock()
1053 current_vddc = current_ps->levels[current_index].vddc_index; in sumo_patch_thermal_state()
1054 current_sclk = current_ps->levels[current_index].sclk; in sumo_patch_thermal_state()
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| D | rv770_dpm.c | 289 smc_state->levels[i].aT = cpu_to_be32(a_t); in rv770_populate_smc_t()
295 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT = in rv770_populate_smc_t()
309 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in rv770_populate_smc_sp()
311 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP = in rv770_populate_smc_sp()
685 &smc_state->levels[0], in rv770_convert_power_state_to_smc()
692 &smc_state->levels[1], in rv770_convert_power_state_to_smc()
699 &smc_state->levels[2], in rv770_convert_power_state_to_smc()
704 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in rv770_convert_power_state_to_smc()
705 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in rv770_convert_power_state_to_smc()
706 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in rv770_convert_power_state_to_smc()
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| D | trinity_dpm.c | 849 trinity_program_power_level(rdev, &new_ps->levels[i], i); in trinity_program_power_levels_0_to_n()
969 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
970 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
983 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
984 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1331 ps->levels[0] = pi->boot_pl; in trinity_patch_boot_state()
1354 pi->current_ps.levels[0] = pi->boot_pl; in trinity_construct_boot_state()
1409 current_vddc = current_ps->levels[current_index].vddc_index; in trinity_patch_thermal_state()
1410 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()
1416 ps->levels[0].vddc_index = current_vddc; in trinity_patch_thermal_state()
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| D | ni_dpm.c | 1691 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in ni_populate_smc_initial_state()
1693 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1695 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in ni_populate_smc_initial_state()
1697 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1699 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in ni_populate_smc_initial_state()
1701 table->initialState.levels[0].mclk.vDLL_CNTL = in ni_populate_smc_initial_state()
1703 table->initialState.levels[0].mclk.vMPLL_SS = in ni_populate_smc_initial_state()
1705 table->initialState.levels[0].mclk.vMPLL_SS2 = in ni_populate_smc_initial_state()
1707 table->initialState.levels[0].mclk.mclk_value = in ni_populate_smc_initial_state()
1710 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in ni_populate_smc_initial_state()
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| D | si_dpm.c | 2299 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2300 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2301 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2302 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2303 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2353 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2354 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2355 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2356 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2357 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
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| /kernel/linux/linux-5.10/drivers/video/backlight/ |
| D | pwm_bl.c | 26 unsigned int *levels; member
97 if (pb->levels) in compute_duty_cycle()
98 duty_cycle = pb->levels[brightness]; in compute_duty_cycle()
208 data->levels = devm_kcalloc(dev, data->max_brightness, in pwm_backlight_brightness_default()
209 sizeof(*data->levels), GFP_KERNEL); in pwm_backlight_brightness_default()
210 if (!data->levels) in pwm_backlight_brightness_default()
220 data->levels[i] = (unsigned int)retval; in pwm_backlight_brightness_default()
267 size_t size = sizeof(*data->levels) * data->max_brightness; in pwm_backlight_parse_dt()
270 data->levels = devm_kzalloc(dev, size, GFP_KERNEL); in pwm_backlight_parse_dt()
271 if (!data->levels) in pwm_backlight_parse_dt()
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| D | led_bl.c | 20 unsigned int *levels; member
30 if (priv->levels) in led_bl_set_brightness()
31 bkl_brightness = priv->levels[level]; in led_bl_set_brightness()
138 u32 *levels = NULL; in led_bl_parse_levels() local
140 levels = devm_kzalloc(dev, sizeof(u32) * num_levels, in led_bl_parse_levels()
142 if (!levels) in led_bl_parse_levels()
146 levels, in led_bl_parse_levels()
157 if ((i && db > levels[i-1]) && db <= levels[i]) in led_bl_parse_levels()
162 priv->levels = levels; in led_bl_parse_levels()
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/powernv/ |
| D | pci-ioda-tce.c | 81 unsigned long size, unsigned int levels);
218 unsigned long size, unsigned int levels) in pnv_pci_ioda2_table_do_free_pages() argument
223 if (levels) { in pnv_pci_ioda2_table_do_free_pages()
234 levels - 1); in pnv_pci_ioda2_table_do_free_pages()
258 unsigned int levels, unsigned long limit, in pnv_pci_ioda2_table_do_alloc_pages() argument
269 --levels; in pnv_pci_ioda2_table_do_alloc_pages()
270 if (!levels) { in pnv_pci_ioda2_table_do_alloc_pages()
277 levels, limit, current_offset, total_allocated); in pnv_pci_ioda2_table_do_alloc_pages()
292 __u32 page_shift, __u64 window_size, __u32 levels, in pnv_pci_ioda2_table_alloc_pages() argument
304 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) in pnv_pci_ioda2_table_alloc_pages()
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| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | cacheinfo.c | 121 int levels = 0, leaves = 0, level; in init_cache_level() local
130 levels = 1; in init_cache_level()
140 if (level <= levels) in init_cache_level()
148 levels = level; in init_cache_level()
152 this_cpu_ci->num_levels = levels; in init_cache_level()
164 int levels = 1, level = 1; in populate_cache_leaves() local
179 if (level <= levels) in populate_cache_leaves()
184 levels = level; in populate_cache_leaves()
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | cacheinfo.c | 24 int levels = 0, leaves = 0; in init_cache_level() local
31 levels += 1; in init_cache_level()
39 levels++; in init_cache_level()
44 levels++; in init_cache_level()
48 this_cpu_ci->num_levels = levels; in init_cache_level()
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| /kernel/linux/linux-5.10/Documentation/scheduler/ |
| D | sched-nice-design.rst | 6 nice-levels implementation in the new Linux scheduler.
8 Nice levels were always pretty weak under Linux and people continuously
16 In the O(1) scheduler (in 2003) we changed negative nice levels to be
58 To sum it up: we always wanted to make nice levels more consistent, but
83 nice levels were not 'punchy enough', so lots of people had to resort to
90 To address the first complaint (of nice levels being not "punchy"
92 (and granularity was made a separate concept from nice levels) and thus
98 To address the second complaint (of nice levels not being consistent),
100 tasks, regardless of their absolute nice levels. So on the new
104 levels were changed to be "multiplicative" (or exponential) - that way
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| /kernel/linux/linux-5.10/drivers/acpi/ |
| D | acpi_video.c | 238 if (vd->brightness->levels[i] == cur_level) in acpi_video_get_brightness()
251 vd->brightness->levels[request_level]); in acpi_video_set_brightness()
282 if (level == video->brightness->levels[offset]) { in video_get_cur_state()
301 level = video->brightness->levels[state - 1]; in video_set_cur_state()
319 union acpi_object **levels) in acpi_video_device_lcd_query_levels() argument
326 *levels = NULL; in acpi_video_device_lcd_query_levels()
338 *levels = obj; in acpi_video_device_lcd_query_levels()
364 if (level == device->brightness->levels[state]) { in acpi_video_device_lcd_set_level()
605 level = device->brightness->levels[bqc_value + in acpi_video_bqc_value_to_level()
642 if (device->brightness->levels[i] == *level) { in acpi_video_device_lcd_get_level_current()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/ |
| D | si_dpm.c | 2395 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2396 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2397 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2398 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2399 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2448 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2449 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2450 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2451 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2452 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
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| /kernel/linux/linux-5.10/drivers/thermal/intel/int340x_thermal/ |
| D | int3406_thermal.c | 60 acpi_level = d->br->levels[d->upper_limit - state]; in int3406_thermal_set_cur_state()
83 if (acpi_level <= d->br->levels[index]) in int3406_thermal_get_cur_state()
115 d->lower_limit = int3406_thermal_get_index(d->br->levels, in int3406_thermal_get_limit()
120 d->upper_limit = int3406_thermal_get_index(d->br->levels, in int3406_thermal_get_limit()
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| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-class-backlight-adp5520 | 4 The backlight brightness control operates at three different levels for the
16 is at one of the three levels (daylight, office or dark). This
29 one of the three levels (daylight, office or dark). This is an
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| D | sysfs-class-backlight-adp8860 | 4 The backlight brightness control operates at three different levels for the
21 is at one of the three levels (daylight, office or dark). This
35 one of the three levels (daylight, office or dark). This is an
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| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| D | kvm_arm.h | 185 #define VTCR_EL2_LVLS_TO_SL0(levels) \ argument
186 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
258 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) argument
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| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | memory.rst | 8 Linux kernel. The architecture allows up to 4 levels of translation
9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
48 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
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| /kernel/linux/linux-5.10/Documentation/ABI/ |
| D | README | 3 everchanging nature of Linux, and the differing maturity levels, these
6 We have four different levels of ABI stability, as shown by the four
7 different subdirectories in this location. Interfaces may change levels
10 The different levels of stability are:
69 How things move between levels:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/hwmon/ |
| D | aspeed-pwm-tacho.txt | 34 For PWM port can be configured cooling-levels to create cooling device.
42 - cooling-levels: PWM duty cycle values in a range from 0 to 255
65 cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
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| D | npcm750-pwm-fan.txt | 28 For PWM channel can be configured cooling-levels to create cooling device.
43 - cooling-levels: PWM duty cycle values in a range from 0 to 255
73 cooling-levels = <127 255>;
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | fiji_smumgr.c | 1015 struct SMU73_Discrete_GraphicsLevel *levels = in fiji_populate_all_graphic_levels() local
1026 &levels[i]); in fiji_populate_all_graphic_levels()
1032 levels[i].DeepSleepDivId = 0; in fiji_populate_all_graphic_levels()
1036 levels[0].EnabledForActivity = 1; in fiji_populate_all_graphic_levels()
1039 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1053 levels[i].pcieDpmLevel = in fiji_populate_all_graphic_levels()
1078 levels[i].pcieDpmLevel = hightest_pcie_level_enabled; in fiji_populate_all_graphic_levels()
1081 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; in fiji_populate_all_graphic_levels()
1084 levels[1].pcieDpmLevel = mid_pcie_level_enabled; in fiji_populate_all_graphic_levels()
1087 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, in fiji_populate_all_graphic_levels()
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