| /kernel/linux/linux-5.10/drivers/clk/pistachio/ |
| D | clk-pll.c | 241 params->postdiv2 != old_postdiv2)) in pll_gf40lp_frac_set_rate()
244 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_frac_set_rate()
254 (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
282 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
387 params->postdiv2 != old_postdiv2)) in pll_gf40lp_laint_set_rate()
390 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_laint_set_rate()
400 (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
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| D | clk.h | 100 unsigned long long postdiv2; member
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-pll.c | 153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
184 do_div(rate64, cur.postdiv2); in rockchip_rk3036_pll_recalc_rate()
202 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
325 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
633 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3399_pll_get_params()
666 do_div(rate64, cur.postdiv2); in rockchip_rk3399_pll_recalc_rate()
684 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
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| D | clk.h | 205 .postdiv2 = _postdiv2, \
254 unsigned int postdiv2; member
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| /kernel/linux/linux-5.10/arch/mips/ar7/ |
| D | clock.c | 73 u32 postdiv2; member
262 int prediv, int postdiv, int postdiv2, int mul, u32 frequency) in tnetd7200_set_clock() argument
267 base, frequency, prediv, postdiv, postdiv2, mul); in tnetd7200_set_clock()
284 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); in tnetd7200_set_clock()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_28nm_8960.c | 54 u8 postdiv2; member
345 cached_state->postdiv2 = in dsi_pll_28nm_save_state()
371 cached_state->postdiv2); in dsi_pll_28nm_restore_state()
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-bm1880.c | 478 u32 postdiv1, postdiv2, denominator; in bm1880_pll_rate_calc() local
483 postdiv2 = (regval >> 12) & 0x7; in bm1880_pll_rate_calc()
486 denominator = refdiv * postdiv1 * postdiv2; in bm1880_pll_rate_calc()
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| /kernel/linux/patches/linux-5.10/yangfan_patch/ |
| D | drivers.patch | 882 + u32 *postdiv2,
889 + for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
890 + freq = fout_hz * (*postdiv1) * (*postdiv2);
902 + *postdiv2 = 1;
916 + u32 f_frac, postdiv1, postdiv2;
922 + rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
924 + rate_table->postdiv2 = postdiv2;
936 + pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u, fbdiv = %u, postdiv1 = %u, postdiv2…
939 + rate_table->postdiv2, rate_table->frac);
945 + pr_debug("frac get postdiv1 = %u, postdiv2 = %u, foutvco = %u\n",
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| /kernel/linux/patches/linux-5.10/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 17104 + intf_sync_attr.user_intf_sync_attr.user_sync_pll.postdiv2 = 7;
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| /kernel/linux/patches/linux-4.19/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 300141 + intf_sync_attr.user_intf_sync_attr.user_sync_pll.postdiv2 = 7;
|