| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 24 ADDC = 0x01, enumerator
80 case ADDC: in lanaiAluCodeToString()
106 .Case("addc", ADDC) in stringToLanaiAluCode()
123 return AluCode::ADDC; in isdToLanaiAluCode()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 224 ADDC, SUBC, enumerator
|
| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/ |
| D | comc597.mme.h | 781 ADDC, ZERO, R7, ZERO, (1<<12)|0x1b00/4, NONE, ALU0),
864 ADDC, R4, R4, R2, 0, NONE, ALU1),
885 ADDC, R2, R2, R4, 0, NONE, NONE),
899 ADDC, ZERO, R3, ZERO, (1<<12)|0x1b00/4, NONE, ALU0),
|
| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 223 EMIT2(ADDC)
|
| D | brw_vec4_builder.h | 397 ALU2_ACC(ADDC) in ALU2_ACC() argument
|
| D | brw_fs_builder.h | 605 ALU2_ACC(ADDC) in ALU3()
|
| D | brw_eu.h | 280 ALU2(ADDC) in ALU2()
|
| D | brw_vec4_visitor.cpp | 187 ALU2_ACC(ADDC) in ALU1()
|
| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 96 …return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DRF… in emit_single_op()
|
| D | sljitNativePPC_32.c | 121 return push_inst(compiler, ADDC | RC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| D | sljitNativePPC_64.c | 253 return push_inst(compiler, ADDC | RC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| /third_party/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 54 addc { yylval.integer = BRW_OPCODE_ADDC; return ADDC; }
|
| D | i965_gram.y | 385 %token <integer> ADD ADD3 ADDC AND ASR AVG
768 ADDC
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 38 ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout). enumerator
|
| D | HexagonISelDAGToDAG.cpp | 763 unsigned OpcCarry = N->getOpcode() == HexagonISD::ADDC ? Hexagon::A4_addp_c in SelectAddSubCarry()
890 case HexagonISD::ADDC: in Select()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 104 ADDC, // Add with carry enumerator
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenFastISel.inc | 1815 // FastEmit functions for ISD::ADDC.
1820 return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3279 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3455 // FastEmit functions for ISD::ADDC.
3508 …case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
3530 // FastEmit functions for ISD::ADDC.
3565 …case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 289 case ISD::ADDC: return "addc"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 1886 case ISD::ADDC: in ExpandIntegerResult()
2288 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
2294 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
2390 if (N->getOpcode() == ISD::ADDC) { in ExpandIntRes_ADDSUBC()
2391 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 757 case ISD::ADDC: in Select()
1005 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; in SelectADD_SUB_I64()
1006 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 134 (instregex "ADDC(8)?(O)?$"),
1043 (instregex "ADDC(8)?(O)?_rec$"),
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1548 setOperationAction(ISD::ADDC, MVT::i32, Custom); in SparcTargetLowering()
1554 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
2904 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3052 case ISD::ADDC: in LowerOperation()
|
| /third_party/skia/third_party/externals/opengl-registry/extensions/NV/ |
| D | NV_vertex_program3.txt | 301 "ADDC", "ADDC0", "ADDC1", "ADD_SAT", "ADDC_SAT", "ADDC0_SAT", and
413 The instruction "ADDC" will update the condition code; the otherwise
|
| /third_party/openGLES/extensions/NV/ |
| D | NV_vertex_program3.txt | 301 "ADDC", "ADDC0", "ADDC1", "ADD_SAT", "ADDC_SAT", "ADDC0_SAT", and
413 The instruction "ADDC" will update the condition code; the otherwise
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 214 if (Opc == ISD::ADDC) { in selectAddE()
|