| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 150 const MachineOperand *BaseOp; in runOnMachineFunction() local
152 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI) && in runOnMachineFunction()
153 BaseOp->isReg()) { in runOnMachineFunction()
154 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction()
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| D | AArch64InstrInfo.h | 116 const MachineOperand *&BaseOp,
121 const MachineOperand *&BaseOp,
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| D | AArch64InstrInfo.cpp | 1982 const MachineOperand *&BaseOp, in getMemOperandWithOffset() argument
1989 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
1993 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
2024 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
2028 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
2032 if (!BaseOp->isReg() && !BaseOp->isFI()) in getMemOperandWithOffsetWidth()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 71 const MachineOperand *&BaseOp,
76 const MachineOperand *&BaseOp,
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| D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
792 if (!BaseOp->isReg()) in getMemOperandWithOffsetWidth()
799 const MachineOperand *&BaseOp, in getMemOperandWithOffset() argument
815 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 1474 const MachineOperand *BaseOp; member
1478 : SU(su), BaseOp(Op), Offset(ofs) {} in MemOpInfo()
1481 if (BaseOp->getType() != RHS.BaseOp->getType()) in operator <()
1482 return BaseOp->getType() < RHS.BaseOp->getType(); in operator <()
1484 if (BaseOp->isReg()) in operator <()
1485 return std::make_tuple(BaseOp->getReg(), Offset, SU->NodeNum) < in operator <()
1486 std::make_tuple(RHS.BaseOp->getReg(), RHS.Offset, in operator <()
1488 if (BaseOp->isFI()) { in operator <()
1490 *BaseOp->getParent()->getParent()->getParent(); in operator <()
1496 if (BaseOp->getIndex() != RHS.BaseOp->getIndex()) in operator <()
[all …]
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| D | ImplicitNullChecks.cpp | 367 const MachineOperand *BaseOp; in isSuitableMemoryOp() local
369 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI) || in isSuitableMemoryOp()
370 !BaseOp->isReg() || BaseOp->getReg() != PointerReg) in isSuitableMemoryOp()
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| D | MachineSink.cpp | 765 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
767 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI)) in SinkingPreventsImplicitNullCheck()
770 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
783 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
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| D | TargetInstrInfo.cpp | 1165 const MachineOperand *BaseOp; in describeLoadedValue() local
1166 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI)) in describeLoadedValue()
1179 return ParamLoadedValue(*BaseOp, Expr); in describeLoadedValue()
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| D | ModuloSchedule.cpp | 914 const MachineOperand *BaseOp; in computeDelta() local
916 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI)) in computeDelta()
919 if (!BaseOp->isReg()) in computeDelta()
922 Register BaseReg = BaseOp->getReg(); in computeDelta()
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| D | MachinePipeliner.cpp | 2059 const MachineOperand *BaseOp; in computeDelta() local
2061 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI)) in computeDelta()
2064 if (!BaseOp->isReg()) in computeDelta()
2067 Register BaseReg = BaseOp->getReg(); in computeDelta()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 363 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1) in processAddUses() local
366 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
418 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1) in updateAddUses() local
422 BaseOp.setReg(newReg); in updateAddUses()
423 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
424 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
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| D | HexagonInstrInfo.cpp | 1062 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1063 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1069 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1077 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1078 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1086 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1091 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1100 const MachineOperand &BaseOp = MI.getOperand(0); in expandPostRAPseudo() local
1101 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1107 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
[all …]
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| D | HexagonInstrInfo.h | 208 const MachineOperand *&BaseOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFMISimplifyPatchable.cpp | 93 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
125 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | EvergreenInstructions.td | 561 field string BaseOp;
570 let BaseOp = name;
576 let BaseOp = name;
592 field string BaseOp;
600 let BaseOp = name;
606 let BaseOp = name;
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| D | SIInstrInfo.cpp | 262 const MachineOperand *&BaseOp, in getMemOperandWithOffset() argument
275 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset()
278 if (!BaseOp || !BaseOp->isReg()) in getMemOperandWithOffset()
313 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset()
314 if (!BaseOp->isReg()) in getMemOperandWithOffset()
342 BaseOp = SOffset; in getMemOperandWithOffset()
353 BaseOp = AddrReg; in getMemOperandWithOffset()
358 if (!BaseOp->isReg()) in getMemOperandWithOffset()
371 BaseOp = SBaseReg; in getMemOperandWithOffset()
373 if (!BaseOp->isReg()) in getMemOperandWithOffset()
[all …]
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| D | SIInstrInfo.h | 185 const MachineOperand *&BaseOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.h | 90 const MachineOperand *&BaseOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1521 const MachineOperand &BaseOp = MI.getOperand(2); in MergeBaseUpdateLSDouble() local
1522 Register Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1550 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define); in MergeBaseUpdateLSDouble()
1553 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op); in MergeBaseUpdateLSDouble()
1555 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1664 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local
1665 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1690 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1691 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 363 const MachineOperand *&BaseOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 295 const MachineOperand *&BaseOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 1568 // let RowFields = BaseOp
1569 // All add instruction predicated/non-predicated will have to set their BaseOp
1572 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1573 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1574 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1245 const MachineOperand *&BaseOp, in getMemOperandWithOffset() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3600 unsigned BaseOp = 0; in lowerXALUO() local
3607 BaseOp = SystemZISD::SADDO; in lowerXALUO()
3612 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
3617 BaseOp = SystemZISD::UADDO; in lowerXALUO()
3622 BaseOp = SystemZISD::USUBO; in lowerXALUO()
3629 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerXALUO()
3665 unsigned BaseOp = 0; in lowerADDSUBCARRY() local
3675 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
3683 BaseOp = SystemZISD::SUBCARRY; in lowerADDSUBCARRY()
3695 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry); in lowerADDSUBCARRY()
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