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Searched refs:DIV_ROUND_UP (Results 1 – 25 of 233) sorted by relevance

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/third_party/mesa3d/src/freedreno/vulkan/
Dtu_util.c95 tiling->tile0.width = util_align_npot(DIV_ROUND_UP(fb->width, 2), tile_align_w); in tu_tiling_config_update_tile_layout()
96 tiling->tile0.height = align(DIV_ROUND_UP(fb->height, 2), tile_align_h); in tu_tiling_config_update_tile_layout()
103 util_align_npot(DIV_ROUND_UP(fb->width, tiling->tile_count.width), tile_align_w); in tu_tiling_config_update_tile_layout()
110 util_align_npot(DIV_ROUND_UP(fb->height, tiling->tile_count.height), tile_align_h); in tu_tiling_config_update_tile_layout()
118 util_align_npot(DIV_ROUND_UP(fb->width, tiling->tile_count.width), tile_align_w); in tu_tiling_config_update_tile_layout()
124 align(DIV_ROUND_UP(fb->height, tiling->tile_count.height), tile_align_h); in tu_tiling_config_update_tile_layout()
146 DIV_ROUND_UP(tiling->tile_count.width, tiling->pipe0.width); in tu_tiling_config_update_pipe_layout()
150 DIV_ROUND_UP(tiling->tile_count.height, tiling->pipe0.height); in tu_tiling_config_update_pipe_layout()
Dtu_image.c544 unsigned lrz_pitch = align(DIV_ROUND_UP(width, 8), 32); in tu_image_init()
545 unsigned lrz_height = align(DIV_ROUND_UP(height, 8), 16); in tu_image_init()
553 unsigned nblocksx = DIV_ROUND_UP(DIV_ROUND_UP(width, 8), 16); in tu_image_init()
554 unsigned nblocksy = DIV_ROUND_UP(DIV_ROUND_UP(height, 8), 4); in tu_image_init()
557 image->lrz_fc_size = DIV_ROUND_UP(nblocksx * nblocksy, 8); in tu_image_init()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute_blit.c282 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_compute_clear_buffer_rmw()
288 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_compute_clear_buffer_rmw()
316 unsigned size_12 = DIV_ROUND_UP(size, 12); in si_compute_clear_12bytes_buffer()
334 info.grid[0] = DIV_ROUND_UP(size_12, 64); in si_compute_clear_12bytes_buffer()
368 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_compute_do_clear_or_copy()
374 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_compute_do_clear_or_copy()
543 info->grid[i] = DIV_ROUND_UP(work[i], info->block[i]); in set_work_size()
804 unsigned width = DIV_ROUND_UP(tex->buffer.b.b.width0, tex->surface.u.gfx9.color.dcc_block_width); in si_retile_dcc()
805 …unsigned height = DIV_ROUND_UP(tex->buffer.b.b.height0, tex->surface.u.gfx9.color.dcc_block_height… in si_retile_dcc()
813 info.grid[0] = DIV_ROUND_UP(width, info.block[0]); in si_retile_dcc()
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Dsi_sdma_copy_image.c50 return DIV_ROUND_UP(width, blk_w); in minify_as_blocks()
120 unsigned copy_width = DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w); in si_sdma_v4_v5_copy_texture()
121 unsigned copy_height = DIV_ROUND_UP(ssrc->buffer.b.b.height0, ssrc->surface.blk_h); in si_sdma_v4_v5_copy_texture()
156 unsigned tiled_width = DIV_ROUND_UP(tiled->buffer.b.b.width0, tiled->surface.blk_w); in si_sdma_v4_v5_copy_texture()
157 unsigned tiled_height = DIV_ROUND_UP(tiled->buffer.b.b.height0, tiled->surface.blk_h); in si_sdma_v4_v5_copy_texture()
249 unsigned copy_width = DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w); in cik_sdma_copy_texture()
250 unsigned copy_height = DIV_ROUND_UP(ssrc->buffer.b.b.height0, ssrc->surface.blk_h); in cik_sdma_copy_texture()
/third_party/mesa3d/src/intel/common/
Dintel_urb_config.c165 chunks[i] = DIV_ROUND_UP(min_entries[i] * entry_size_bytes[i], in intel_get_urb_config()
169 DIV_ROUND_UP(devinfo->urb.max_entries[i] * entry_size_bytes[i], in intel_get_urb_config()
305 r.task_entry_size_64b = DIV_ROUND_UP(tue_size_dw * 4, 64); in intel_get_mesh_urb_config()
306 r.mesh_entry_size_64b = DIV_ROUND_UP(mue_size_dw * 4, 64); in intel_get_mesh_urb_config()
350 unsigned next_address_8kb = DIV_ROUND_UP(push_constant_kb, 8); in intel_get_mesh_urb_config()
/third_party/mesa3d/src/intel/tools/
Dintel_noop_drm_shim.c269 DIV_ROUND_UP(i915.devinfo.num_slices, 8) + in query_write_topology()
270 i915.devinfo.num_slices * DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8) + in query_write_topology()
272 DIV_ROUND_UP(i915.devinfo.max_eus_per_subslice, 8); in query_write_topology()
293 info->subslice_offset = DIV_ROUND_UP(i915.devinfo.num_slices, 8); in query_write_topology()
294 info->subslice_stride = DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8); in query_write_topology()
296 info->eu_stride = DIV_ROUND_UP(info->max_eus_per_subslice, 8); in query_write_topology()
313 for (uint32_t i = 0; i < DIV_ROUND_UP(info->max_eus_per_subslice, 8); i++) { in query_write_topology()
315 … (s * info->max_subslices + ss) * DIV_ROUND_UP(info->max_eus_per_subslice, 8) + i] = in query_write_topology()
/third_party/mesa3d/src/imagination/vulkan/
Dpvr_job_render.c324 info->num_tiles_x = DIV_ROUND_UP(width, info->tile_size_x); in pvr_rt_mtile_info_init()
325 info->num_tiles_y = DIV_ROUND_UP(height, info->tile_size_y); in pvr_rt_mtile_info_init()
336 info->mtile_x1 = DIV_ROUND_UP(info->num_tiles_x, 8) * 2; in pvr_rt_mtile_info_init()
337 info->mtile_y1 = DIV_ROUND_UP(info->num_tiles_y, 8) * 2; in pvr_rt_mtile_info_init()
346 info->mtile_x1 = ALIGN_POT(DIV_ROUND_UP(info->num_tiles_x, 4), 4); in pvr_rt_mtile_info_init()
347 info->mtile_y1 = ALIGN_POT(DIV_ROUND_UP(info->num_tiles_y, 4), 4); in pvr_rt_mtile_info_init()
395 rgn_size = DIV_ROUND_UP(rgn_size * rgn_header_size, 4); in pvr_rt_get_isp_region_size()
554 num_pte_pages = DIV_ROUND_UP(total_pages, ROGUE_NUM_PT_ENTRIES_PER_PAGE); in pvr_rt_get_mlist_size()
555 num_pde_pages = DIV_ROUND_UP(num_pte_pages, ROGUE_NUM_PD_ENTRIES_PER_PAGE); in pvr_rt_get_mlist_size()
556 num_pce_pages = DIV_ROUND_UP(num_pde_pages, ROGUE_NUM_PC_ENTRIES_PER_PAGE); in pvr_rt_get_mlist_size()
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Dpvr_cmd_buffer.c676 DIV_ROUND_UP(load_op->const_shareds_count, in pvr_pds_bgnd_pack_state()
678 value.pds_texturestatesize = DIV_ROUND_UP( in pvr_pds_bgnd_pack_state()
682 DIV_ROUND_UP(load_op->temps_count, in pvr_pds_bgnd_pack_state()
1152 DIV_ROUND_UP(coeff_regs_count << 2, in pvr_compute_flat_slot_size()
1186 DIV_ROUND_UP(max_avail_coeff_regs * 4U, in pvr_compute_flat_slot_size()
1351 DIV_ROUND_UP(cmd_buffer->device->idfwdf_state.usc_shareds << 2, in pvr_compute_generate_idfwdf()
1356 DIV_ROUND_UP(program->data_size << 2, in pvr_compute_generate_idfwdf()
1396 DIV_ROUND_UP(program->data_size << 2, in pvr_compute_generate_fence()
2956 DIV_ROUND_UP(const_shared_reg_count, in pvr_compute_update_shared()
2974 DIV_ROUND_UP(pds_data_size_in_dwords << 2U, in pvr_compute_update_shared()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_resource.c33 unsigned lrz_pitch = align(DIV_ROUND_UP(rsc->b.b.width0, 8), 64); in setup_lrz()
34 unsigned lrz_height = DIV_ROUND_UP(rsc->b.b.height0, 8); in setup_lrz()
/third_party/mesa3d/src/intel/compiler/
Dbrw_vec4_dead_code_eliminate.cpp60 for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) { in dead_code_eliminate()
142 for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) { in dead_code_eliminate()
164 for (unsigned j = 0; j < DIV_ROUND_UP(inst->size_read(i), 16); j++) { in dead_code_eliminate()
Dbrw_vec4_live_variables.h118 const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
132 const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
Dbrw_fs_bank_conflicts.cpp286 DIV_ROUND_UP(u.size, vector_width) * sizeof(vector_type)); in weight_vector_type()
310 const unsigned size = DIV_ROUND_UP(n, vector_width) * sizeof(vector_type); in alloc()
661 const unsigned cycle_scale = block_scale * DIV_ROUND_UP(exec_size, in shader_conflict_weight_matrix()
709 const unsigned m = DIV_ROUND_UP(conflicts[r].size, vector_width); in have_any_conflicts()
739 const unsigned m = DIV_ROUND_UP(conflicts.size, vector_width); in delta_conflicts()
Dbrw_ir_performance.cpp125 td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)), in instruction_info()
134 ss = DIV_ROUND_UP(inst->size_read(2), REG_SIZE) + in instruction_info()
135 DIV_ROUND_UP(inst->size_read(3), REG_SIZE); in instruction_info()
138 ss = MAX2(ss, DIV_ROUND_UP(inst->size_read(i), REG_SIZE)); in instruction_info()
142 sx = DIV_ROUND_UP(inst->exec_size * type_sz(tx), REG_SIZE); in instruction_info()
156 td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)), in instruction_info()
162 ss = MAX2(ss, DIV_ROUND_UP(inst->size_read(i), REG_SIZE)); in instruction_info()
165 sx = DIV_ROUND_UP(inst->exec_size * type_sz(tx), REG_SIZE); in instruction_info()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_const.c54 .num_unit = DIV_ROUND_UP(sizedwords, 4)), in fd6_emit_const_user()
62 .num_unit = DIV_ROUND_UP(sizedwords, 4)), in fd6_emit_const_user()
74 uint32_t num_unit = DIV_ROUND_UP(sizedwords, 4); in fd6_emit_const_bo()
209 int size_vec4s = DIV_ROUND_UP(v->constant_data_size, 16); in fd6_emit_ubos()
229 int size_vec4s = DIV_ROUND_UP(cb->buffer_size, 16); in fd6_emit_ubos()
/third_party/mesa3d/src/panfrost/shared/
Dpan_tiling.c259 w = DIV_ROUND_UP(w, desc->block.width); in panfrost_access_tiled_image_generic()
260 h = DIV_ROUND_UP(h, desc->block.height); in panfrost_access_tiled_image_generic()
305 unsigned first_full_tile_x = DIV_ROUND_UP(x, TILE_WIDTH) * TILE_WIDTH; in panfrost_access_tiled_image()
306 unsigned first_full_tile_y = DIV_ROUND_UP(y, TILE_HEIGHT) * TILE_HEIGHT; in panfrost_access_tiled_image()
/third_party/mesa3d/src/amd/common/
Dac_gpu_info.c739 info->gart_size_kb = DIV_ROUND_UP(meminfo.gtt.total_heap_size, 1024); in ac_query_gpu_info()
740 info->vram_size_kb = DIV_ROUND_UP(fix_vram_size(meminfo.vram.total_heap_size), 1024); in ac_query_gpu_info()
741 info->vram_vis_size_kb = DIV_ROUND_UP(meminfo.cpu_accessible_vram.total_heap_size, 1024); in ac_query_gpu_info()
1189 DIV_ROUND_UP(info->num_cu, (info->num_se * info->max_sa_per_se * cu_group)) * in ac_query_gpu_info()
1335 …info->memory_bandwidth_gbps = DIV_ROUND_UP(info->memory_freq_mhz_effective * info->memory_bus_widt… in ac_query_gpu_info()
1409 fprintf(f, " l0_cache_size = %i KB\n", DIV_ROUND_UP(info->l1_cache_size, 1024)); in ac_print_gpu_info()
1412 fprintf(f, " l1_cache_size = %i KB\n", DIV_ROUND_UP(info->l1_cache_size, 1024)); in ac_print_gpu_info()
1415 fprintf(f, " l2_cache_size = %i KB\n", DIV_ROUND_UP(info->l2_cache_size, 1024)); in ac_print_gpu_info()
1422 DIV_ROUND_UP(info->vram_size_kb, (1024 * 1024)), in ac_print_gpu_info()
1423 DIV_ROUND_UP(info->vram_size_kb, 1024)); in ac_print_gpu_info()
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/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_dcc_retile.c259 unsigned width = DIV_ROUND_UP(image->info.width, vk_format_get_blockwidth(image->vk.format)); in radv_retile_dcc()
260 unsigned height = DIV_ROUND_UP(image->info.height, vk_format_get_blockheight(image->vk.format)); in radv_retile_dcc()
262 unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width); in radv_retile_dcc()
264 DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height); in radv_retile_dcc()
/third_party/mesa3d/src/panfrost/lib/tests/
Dtest-layout.cpp198 16 * DIV_ROUND_UP(width, sw)); in TEST()
201 DIV_ROUND_UP(width, sw)); in TEST()
230 16 * DIV_ROUND_UP(width, (sw * 8)) * 8 * 8); in TEST()
233 DIV_ROUND_UP(width, sw * 8) * 8); in TEST()
/third_party/mesa3d/src/intel/dev/
Dintel_device_info.c1230 devinfo->eu_slice_stride = DIV_ROUND_UP(16 * 4, 8); in update_from_single_slice_topology()
1231 devinfo->eu_subslice_stride = DIV_ROUND_UP(16, 8); in update_from_single_slice_topology()
1295 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8); in update_from_topology()
1298 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
1299 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
1341 topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8); in update_from_masks()
1342 topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8); in update_from_masks()
1346 uint32_t max_eus_per_subslice = DIV_ROUND_UP(n_eus, n_subslices); in update_from_masks()
1351 topology->max_slices * DIV_ROUND_UP(topology->max_subslices, 8); in update_from_masks()
1352 topology->eu_stride = DIV_ROUND_UP(max_eus_per_subslice, 8); in update_from_masks()
Dintel_device_info.h250 DIV_ROUND_UP(INTEL_DEVICE_MAX_SUBSLICES, 8)];
264 DIV_ROUND_UP(INTEL_DEVICE_MAX_EUS_PER_SUBSLICE, 8)];
/third_party/mesa3d/src/vulkan/runtime/
Dvk_image.c261 extent.width = DIV_ROUND_UP(extent.width, fmt->block.width); in vk_image_extent_to_elements()
262 extent.height = DIV_ROUND_UP(extent.height, fmt->block.height); in vk_image_extent_to_elements()
263 extent.depth = DIV_ROUND_UP(extent.depth, fmt->block.depth); in vk_image_extent_to_elements()
306 DIV_ROUND_UP(row_length, fmt->block.width) * element_size_B; in vk_image_buffer_copy_layout()
308 DIV_ROUND_UP(image_height, fmt->block.height) * (uint64_t)row_stride_B; in vk_image_buffer_copy_layout()
/third_party/mesa3d/src/gallium/drivers/svga/include/
Dsvga3d_surfacedefs.h1199 block_size->width = DIV_ROUND_UP(pixel_size->width, in svga3dsurface_get_size_in_blocks()
1201 block_size->height = DIV_ROUND_UP(pixel_size->height, in svga3dsurface_get_size_in_blocks()
1203 block_size->depth = DIV_ROUND_UP(pixel_size->depth, in svga3dsurface_get_size_in_blocks()
1373 const uint32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block; in svga3dsurface_get_pixel_offset()
1374 const uint32 imgstride = DIV_ROUND_UP(height, bh) * rowstride; in svga3dsurface_get_pixel_offset()
/third_party/mesa3d/src/util/
Du_idalloc.c55 util_idalloc_resize(buf, DIV_ROUND_UP(initial_num_ids, 32)); in util_idalloc_init()
105 unsigned num_alloc = DIV_ROUND_UP(num, 32); in util_idalloc_alloc_range()
/third_party/mesa3d/src/freedreno/computerator/
Da4xx.c183 CP_LOAD_STATE4_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4))); in emit_const()
210 int size = DIV_ROUND_UP(const_state->immediates_count, 4); in cs_const_emit()
270 OUT_RING(ring, A4XX_SSBO_1_1_HEIGHT(DIV_ROUND_UP(sz, 1 << 16)) | in cs_ibo_emit()
/third_party/mesa3d/src/panfrost/lib/
Dpan_scratch.c70 return util_logbase2_ceil(DIV_ROUND_UP(stack_size, 16)); in panfrost_get_stack_shift()

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