| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| D | BasicTTIImpl.h | 1244 ISDs.push_back(ISD::FABS);
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 254 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
403 setOperationAction(ISD::FABS, VT, Expand); in AMDGPUTargetLowering()
500 setTargetDAGCombine(ISD::FABS); in AMDGPUTargetLowering()
1600 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1603 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
2143 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2179 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND_LegalFTRUNC()
3522 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) || in foldFreeOpFromSelect()
3529 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3536 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
[all …]
|
| D | R600Instructions.td | 693 class FABS <RegisterClass rc> : AMDGPUShaderInst <
696 "FABS $dst, $src0",
1219 def FABS_R600 : FABS<R600_Reg32>;
|
| D | SIISelLowering.cpp | 599 setOperationAction(ISD::FABS, MVT::v2f16, Legal); in SITargetLowering()
669 setOperationAction(ISD::FABS, MVT::v4f16, Custom); in SITargetLowering()
682 setOperationAction(ISD::FABS, MVT::v2f16, Custom); in SITargetLowering()
4080 case ISD::FABS: in LowerOperation()
4377 case ISD::FABS: { in ReplaceNodeResults()
7662 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in lowerFDIV_FAST()
8326 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X) in performAndCombine()
8603 case ISD::FABS: in fp16SrcZerosHighBits()
8797 case ISD::FABS: in isCanonicalized()
9287 Vec.getOpcode() == ISD::FABS) && allUsesHaveSourceMods(N)) { in performExtractVectorEltCombine()
[all …]
|
| D | AMDGPUISelDAGToDAG.cpp | 2406 if (Src.getOpcode() == ISD::FABS) { in SelectVOP3ModsImpl()
2441 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1613 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1720 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1723 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1742 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3048 case ISD::FABS: in LowerOperation()
|
| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_target_gv100.cpp | 115 OPINFO(FABS , RIC , NA , NONE, NONE, NONE, NONE);
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 965 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
979 assert(Op0.getOpcode() == ISD::FABS); in PerformDAGCombine()
1013 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
1024 assert(Op0.getOpcode() == ISD::FABS); in PerformDAGCombine()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 67 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
1129 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
1245 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
2106 case ISD::FABS: in PromoteFloatResult()
|
| D | SelectionDAGDumper.cpp | 181 case ISD::FABS: return "fabs"; in getOperationName()
|
| D | DAGCombiner.cpp | 1586 case ISD::FABS: return visitFABS(N); in visit()
11105 FPOpcode = ISD::FABS; in foldBitcastedFPLogic()
11113 FPOpcode = ISD::FABS; in foldBitcastedFPLogic()
11223 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
11239 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
11257 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
12479 TLI.isOperationLegal(ISD::FABS, VT)) { in visitFMUL()
12512 DAG.getNode(ISD::FABS, DL, VT, X)); in visitFMUL()
12514 return DAG.getNode(ISD::FABS, DL, VT, X); in visitFMUL()
12895 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) in visitFCOPYSIGN()
[all …]
|
| D | LegalizeDAG.cpp | 1523 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) && in ExpandFCOPYSIGN()
1525 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag); in ExpandFCOPYSIGN()
3164 case ISD::FABS: in ExpandNode()
4514 case ISD::FABS: in PromoteNode()
|
| D | LegalizeVectorOps.cpp | 411 case ISD::FABS: in LegalizeOp()
|
| D | SelectionDAG.cpp | 4121 case ISD::FABS: in isKnownNeverNaN()
4460 case ISD::FABS: in getNode()
4528 case ISD::FABS: in getNode()
4755 case ISD::FABS: in getNode()
4757 return getNode(ISD::FABS, DL, VT, Operand.getOperand(0)); in getNode()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
|
| D | AArch64SchedCyclone.td | 431 // FABS,FNEG are WriteF
|
| D | AArch64SchedExynosM3.td | 532 def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 123 defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
|
| D | MipsISelLowering.cpp | 362 setOperationAction(ISD::FABS, MVT::f32, Custom); in MipsTargetLowering()
363 setOperationAction(ISD::FABS, MVT::f64, Custom); in MipsTargetLowering()
1233 case ISD::FABS: return lowerFABS(Op, DAG); in LowerOperation()
|
| D | MipsInstrFPU.td | 498 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;
|
| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 89 #define FABS 0x1e60c000 macro
1621 FAIL_IF(push_inst(compiler, (FABS ^ inv_bits) | VD(dst_r) | VN(src))); in sljit_emit_fop1()
|
| D | sljitNativePPC_common.c | 168 #define FABS (HI(63) | LO(264)) macro
1946 FAIL_IF(push_inst(compiler, FABS | FD(dst_r) | FB(src))); in sljit_emit_fop1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 573 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) { in NVPTXTargetLowering()
2103 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A); in LowerFROUND32()
2144 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A); in LowerFROUND64()
|
| /third_party/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 688 #define FABS CHOICE(fabs, fabs, fabs) macro
1401 #define FABS fabs macro
|