| /third_party/ltp/tools/sparse/sparse-src/ |
| D | opcode.def | 21 OPCODE(DIVU, BADOP, BADOP, DIVS, FDIV, 2, OPF_TARGET|OPF_BINOP)
22 OPCODE(DIVS, BADOP, BADOP, DIVU, FDIV, 2, OPF_TARGET|OPF_BINOP)
33 OPCODE(FDIV, BADOP, BADOP, BADOP, BADOP, 2, OPF_TARGET)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 186 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
187 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
188 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
204 { ISD::FDIV, MVT::f32, 17 }, // divss in getArithmeticInstrCost()
205 { ISD::FDIV, MVT::v4f32, 39 }, // divps in getArithmeticInstrCost()
206 { ISD::FDIV, MVT::f64, 32 }, // divsd in getArithmeticInstrCost()
207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd in getArithmeticInstrCost()
702 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
703 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
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| D | X86IntrinsicsInfo.h | 449 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
450 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 41 INSTRUCTION(FDiv, 2, 1, experimental_constrained_fdiv, FDIV)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 295 FADD, FSUB, FMUL, FDIV, FREM, enumerator
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| /third_party/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 137 fdiv { yylval.integer = BRW_MATH_FUNCTION_FDIV; return FDIV; }
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| D | i965_gram.y | 405 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
859 | FDIV
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenSubtargetInfo.inc | 3649 { 1, 40, 49, 429, 432 }, // 259 FDIV
3968 { 1, 93, 94, 0, 0 }, // 259 FDIV
4287 { 1, 113, 114, 0, 0 }, // 259 FDIV
4606 { 1, 137, 138, 0, 0 }, // 259 FDIV
4925 { 1, 160, 161, 0, 0 }, // 259 FDIV
5244 { 1, 185, 186, 1009, 1012 }, // 259 FDIV
5563 { 1, 197, 199, 1441, 1444 }, // 259 FDIV
5882 { 1, 231, 233, 1889, 1892 }, // 259 FDIV
6201 { 1, 272, 274, 2408, 2411 }, // 259 FDIV
6520 { 1, 321, 323, 3050, 3053 }, // 259 FDIV
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 705 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } in visitFDiv()
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| D | SelectionDAGDumper.cpp | 254 case ISD::FDIV: return "fdiv"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 81 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; in SoftenFloatResult()
1143 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; in ExpandFloatResult()
2127 case ISD::FDIV: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 380 case ISD::FDIV: in LegalizeOp()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetTransformInfo.cpp | 416 case ISD::FDIV: in getArithmeticInstrCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 36 defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
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| D | MipsSEISelLowering.cpp | 135 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
389 setOperationAction(ISD::FDIV, Ty, Legal); in addMSAFloatType()
1868 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| D | MipsInstrFPU.td | 639 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1714 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1739 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1791 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
3044 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 94 #define FDIV 0x1e601800 macro
1668 FAIL_IF(push_inst(compiler, (FDIV ^ inv_bits) | VD(dst_r) | VN(src1) | VM(src2))); in sljit_emit_fop2()
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| D | sljitNativePPC_common.c | 175 #define FDIV (HI(63) | LO(18)) macro
1994 FAIL_IF(push_inst(compiler, SELECT_FOP(op, FDIVS, FDIV) | FD(dst_r) | FA(src1) | FB(src2))); in sljit_emit_fop2()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 548 // FDIV,FSQRT
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| D | AArch64ISelLowering.cpp | 262 setOperationAction(ISD::FDIV, MVT::f128, Custom); in AArch64TargetLowering()
441 setOperationAction(ISD::FDIV, MVT::f16, Promote); in AArch64TargetLowering()
461 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); in AArch64TargetLowering()
465 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
487 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); in AArch64TargetLowering()
640 setTargetDAGCombine(ISD::FDIV); in AArch64TargetLowering()
710 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
3202 case ISD::FDIV: in LowerOperation()
12565 case ISD::FDIV: in PerformDAGCombine()
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| D | AArch64SchedA57.td | 456 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1603 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 640 setOperationAction(ISD::FDIV, VT, Expand); in PPCTargetLowering()
740 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
806 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
914 setOperationAction(ISD::FDIV, MVT::f128, Legal); in PPCTargetLowering()
1108 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); in PPCTargetLowering()
1111 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
1114 setOperationAction(ISD::FDIV, MVT::v4f64, Expand); in PPCTargetLowering()
1117 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in PPCTargetLowering()
1184 setTargetDAGCombine(ISD::FDIV); in PPCTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 208 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in WebAssemblyTargetLowering()
|