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Searched refs:FDIVS (Results 1 – 19 of 19) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DLeonFeatures.td58 "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
DSparcInstrInfo.td1274 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
1276 def FDIVS : F3_3<2, 0b110100, 0b001001101,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenSubtargetInfo.inc3660 { 1, 49, 58, 438, 441 }, // 270 FDIVS
3979 { 1, 94, 95, 0, 0 }, // 270 FDIVS
4298 { 1, 116, 117, 0, 0 }, // 270 FDIVS
4617 { 1, 140, 141, 0, 0 }, // 270 FDIVS
4936 { 1, 160, 161, 0, 0 }, // 270 FDIVS
5255 { 1, 185, 186, 1042, 1045 }, // 270 FDIVS
5574 { 1, 203, 205, 1450, 1453 }, // 270 FDIVS
5893 { 1, 235, 237, 1898, 1901 }, // 270 FDIVS
6212 { 1, 274, 276, 2417, 2420 }, // 270 FDIVS
6531 { 1, 321, 323, 3083, 3086 }, // 270 FDIVS
[all …]
DPPCGenMCCodeEmitter.inc931 UINT64_C(3959423012), // FDIVS
3404 case PPC::FDIVS:
7341 CEFBS_None, // FDIVS = 918
DPPCGenInstrInfo.inc933 FDIVS = 918,
2587 FDIVS = 270,
3902 …, 4, 270, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #918 = FDIVS
12645 { PPC::FDIVS_rec, PPC::FDIVS },
12847 { PPC::FDIVS, PPC::FDIVS_rec },
DPPCGenFastISel.inc2017 return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DPPCGenAsmWriter.inc2586 26055U, // FDIVS
4877 38U, // FDIVS
DPPCGenDisassemblerTables.inc2390 /* 11136 */ MCD::OPC_Decode, 150, 7, 126, // Opcode: FDIVS
DPPCGenAsmMatcher.inc5670 …{ 5970 /* fdivs */, PPC::FDIVS, Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2, AMFBS_None, { MCK_Reg…
DPPCGenDAGISel.inc38564 /* 97677*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::FDIVS), 0,
38567 // Dst: (FDIVS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB)
/third_party/pcre2/pcre2/src/sljit/
DsljitNativeSPARC_common.c145 #define FDIVS (OPC1(0x2) | OPC3(0x34) | DOP(0x4d)) macro
1335 …FAIL_IF(push_inst(compiler, SELECT_FOP(op, FDIVS, FDIVD) | FD(dst_r) | FS1(src1) | FS2(src2), MOVA… in sljit_emit_fop2()
DsljitNativePPC_common.c176 #define FDIVS (HI(59) | LO(18)) macro
1994 FAIL_IF(push_inst(compiler, SELECT_FOP(op, FDIVS, FDIV) | FD(dst_r) | FA(src1) | FB(src2))); in sljit_emit_fop2()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h577 X86ISD::FDIVS, X86ISD::FDIVS_RND),
579 X86ISD::FDIVS, X86ISD::FDIVS_RND),
DX86ISelLowering.h210 FDIV_RND, FDIVS, FDIVS_RND, enumerator
DX86InstrFragmentsSIMD.td514 def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>;
DX86ISelLowering.cpp29876 case X86ISD::FDIVS: return "X86ISD::FDIVS"; in getTargetNodeName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DP9InstrResources.td1204 FDIVS
DPPCInstrInfo.td3008 defm FDIVS : AForm_2r<59, 18,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc11186 // FastEmit functions for X86ISD::FDIVS.
15157 case X86ISD::FDIVS: return fastEmit_X86ISD_FDIVS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);