| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 426 setOperationAction(ISD::FNEG, VT, Expand); in AMDGPUTargetLowering()
499 setTargetDAGCombine(ISD::FNEG); in AMDGPUTargetLowering()
1585 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2477 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
3523 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
3529 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3536 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
3548 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc)) in foldFreeOpFromSelect()
3555 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
3556 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
[all …]
|
| D | AMDGPUISelDAGToDAG.cpp | 2401 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3ModsImpl()
2441 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
2474 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2485 if (Lo.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2490 if (Hi.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
|
| D | R600Instructions.td | 700 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
703 "FNEG $dst, $src0",
1220 def FNEG_R600 : FNEG<R600_Reg32>;
|
| D | SIISelLowering.cpp | 596 setOperationAction(ISD::FNEG, MVT::v2f16, Legal); in SITargetLowering()
668 setOperationAction(ISD::FNEG, MVT::v4f16, Custom); in SITargetLowering()
681 setOperationAction(ISD::FNEG, MVT::v2f16, Custom); in SITargetLowering()
4081 case ISD::FNEG: in LowerOperation()
4364 case ISD::FNEG: { in ReplaceNodeResults()
7579 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
7723 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32()
7821 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64()
8796 case ISD::FNEG: in isCanonicalized()
9286 if ((Vec.getOpcode() == ISD::FNEG || in performExtractVectorEltCombine()
[all …]
|
| /third_party/ltp/tools/sparse/sparse-src/ |
| D | opcode.def | 73 OPCODE(NEG, BADOP, BADOP, BADOP, FNEG, 1, OPF_TARGET|OPF_UNOP)
74 OPCODE(FNEG, BADOP, BADOP, BADOP, BADOP, 1, OPF_TARGET)
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1585 case ISD::FNEG: return visitFNEG(N); in visit()
11109 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
11132 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp); in foldBitcastedFPLogic()
11222 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
11235 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
11254 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
11779 DAG.getNode(ISD::FNEG, SL, VT, N1), Flags); in visitFSUBForFMACombine()
11786 DAG.getNode(ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
11792 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
11797 DAG.getNode(ISD::FNEG, SL, VT, N00), N01, in visitFSUBForFMACombine()
[all …]
|
| D | LegalizeFloatTypes.cpp | 100 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
1162 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1248 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1413 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1414 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
2117 case ISD::FNEG: in PromoteFloatResult()
|
| D | LegalizeVectorOps.cpp | 410 case ISD::FNEG: in LegalizeOp()
875 case ISD::FNEG: in Expand()
1425 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
|
| D | SelectionDAGBuilder.h | 690 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } in visitFNeg()
|
| D | SelectionDAGDumper.cpp | 192 case ISD::FNEG: return "fneg"; in getOperationName()
|
| D | LegalizeDAG.cpp | 1524 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) { in ExpandFCOPYSIGN()
1526 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue); in ExpandFCOPYSIGN()
3156 case ISD::FNEG: in ExpandNode()
3255 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode()
3257 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); in ExpandNode()
4507 case ISD::FNEG: in PromoteNode()
|
| D | SelectionDAG.cpp | 4122 case ISD::FNEG: in isKnownNeverNaN()
4457 case ISD::FNEG: in getNode()
4527 case ISD::FNEG: in getNode()
4747 case ISD::FNEG: in getNode()
4752 if (OpOpcode == ISD::FNEG) // --X -> X in getNode()
4756 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) in getNode()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1612 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1719 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1722 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1741 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3049 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
|
| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_target_gv100.cpp | 117 OPINFO(FNEG , RIC , NA , NONE, NONE, NONE, NONE);
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 965 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
974 if (Op0.getOpcode() == ISD::FNEG) { in PerformDAGCombine()
1013 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
1019 if (Op0.getOpcode() == ISD::FNEG) { in PerformDAGCombine()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
|
| D | AArch64SchedCyclone.td | 431 // FABS,FNEG are WriteF
|
| D | AArch64SchedExynosM3.td | 540 def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 161 defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
|
| D | MipsInstrFPU.td | 504 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 188 (instregex "FNEG(D|S)$"),
1057 (instregex "FNEG(D|S)_rec$"),
|
| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 97 #define FNEG 0x1e614000 macro
1618 FAIL_IF(push_inst(compiler, (FNEG ^ inv_bits) | VD(dst_r) | VN(src))); in sljit_emit_fop1()
|
| D | sljitNativePPC_common.c | 180 #define FNEG (HI(63) | LO(40)) macro
1943 FAIL_IF(push_inst(compiler, FNEG | FD(dst_r) | FB(src))); in sljit_emit_fop1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1594 case FNeg: return ISD::FNEG; in InstructionOpcodeToISD()
|