Searched refs:FSHR (Results 1 – 13 of 13) sorted by relevance
471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator
389 case ISD::FSHR: in LegalizeOp()914 case ISD::FSHR: in Expand()
247 case ISD::FSHR: return "fshr"; in getOperationName()
1199 case ISD::FSHR: in LegalizeOp()3401 case ISD::FSHR: in ExpandNode()
3110 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()3112 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
1540 case ISD::FSHR: { in SimplifyDemandedBits()7256 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
2922 case ISD::FSHR: in computeKnownBits()
6353 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
1545 case ISD::FSHR: return visitFunnelShift(N); in visit()
652 setOperationAction(ISD::FSHR, VT, Expand); in initActions()
1424 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()1425 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
370 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
208 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()1639 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()1844 setOperationAction(ISD::FSHR, MVT::v32i16, Custom); in X86TargetLowering()1900 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()18504 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in LowerShiftParts()18531 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()18539 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift()28564 case ISD::FSHR: return LowerFunnelShift(Op, Subtarget, DAG); in LowerOperation()40631 !TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) in combineOrShiftToFunnelShift()40688 Opc = ISD::FSHR; in combineOrShiftToFunnelShift()[all …]