| /third_party/ltp/tools/sparse/sparse-src/ |
| D | opcode.def | 20 OPCODE(SUB, BADOP, BADOP, BADOP, FSUB, 2, OPF_TARGET|OPF_BINOP)
31 OPCODE(FSUB, BADOP, BADOP, BADOP, BADOP, 2, OPF_TARGET)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 39 INSTRUCTION(FSub, 2, 1, experimental_constrained_fsub, FSUB)
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.h | 195 A_ALU2(FSUB)
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| D | vc4_qpu_emit.c | 259 A(FSUB), in vc4_generate_code_block()
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| D | vc4_qir.h | 675 QIR_ALU2(FSUB) in QIR_ALU1()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 295 FADD, FSUB, FMUL, FDIV, FREM, enumerator
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| D | TargetLowering.h | 2285 case ISD::FSUB: in isBinOp()
2532 assert(N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB); in isFMADLegalForFAddFSub()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd in getArithmeticInstrCost()
544 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
548 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
697 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
698 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
757 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
758 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
759 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
840 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
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| D | X86IntrinsicsInfo.h | 922 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
923 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 378 case ISD::FSUB: in LegalizeOp()
878 case ISD::FSUB: in Expand()
1409 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { in ExpandFNEG()
1413 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero, in ExpandFNEG()
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| D | SelectionDAGBuilder.cpp | 3003 visitBinary(I, ISD::FSUB); in visitFSub()
4980 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
5117 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5134 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5140 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5159 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5165 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5171 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in expandLog()
5213 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5230 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
[all …]
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| D | TargetLowering.cpp | 2548 case ISD::FSUB: in SimplifyDemandedVectorElts()
5534 if (LegalOperations && !isOperationLegalOrCustom(ISD::FSUB, VT)) in isNegatibleForFree()
5544 case ISD::FSUB: in isNegatibleForFree()
5637 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in getNegatedExpression()
5643 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in getNegatedExpression()
5648 case ISD::FSUB: in getNegatedExpression()
5656 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in getNegatedExpression()
6171 SDValue Val = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, FltOfs); in expandFP_TO_UINT()
6184 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst)); in expandFP_TO_UINT()
6271 !isOperationLegalOrCustom(ISD::FSUB, DstVT) || in expandUINT_TO_FP()
[all …]
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| D | SelectionDAGDumper.cpp | 250 case ISD::FSUB: return "fsub"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 121 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult()
1178 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult()
2135 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break; in PromoteFloatResult()
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| D | LegalizeDAG.cpp | 2415 Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); in ExpandLegalINT_TO_FP()
3160 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, in ExpandNode()
3252 case ISD::FSUB: { in ExpandNode()
4142 case ISD::FSUB: in ConvertNodeToLibcall()
4447 case ISD::FSUB: in PromoteNode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 276 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
425 setOperationAction(ISD::FSUB, VT, Expand); in AMDGPUTargetLowering()
498 setTargetDAGCombine(ISD::FSUB); in AMDGPUTargetLowering()
514 case ISD::FSUB: in fnegFoldsIntoOp()
2036 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); in LowerFREM()
2141 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2177 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND_LegalFTRUNC()
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| D | AMDGPUTargetTransformInfo.cpp | 405 case ISD::FSUB: in getArithmeticInstrCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
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| D | AArch64SchedA57.td | 428 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
430 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
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| D | AArch64SchedKryoDetails.td | 639 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
669 (instregex "(FADD|FSUB)(D|S)rr")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativePPC_common.c | 182 #define FSUB (HI(63) | LO(20)) macro
1877 FAIL_IF(push_inst(compiler, FSUB | FD(dst_r) | FA(TMP_FREG1) | FB(TMP_FREG2))); in sljit_emit_fop1_conv_f64_from_sw()
1986 FAIL_IF(push_inst(compiler, SELECT_FOP(op, FSUBS, FSUB) | FD(dst_r) | FA(src1) | FB(src2))); in sljit_emit_fop2()
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| D | sljitNativeARM_64.c | 98 #define FSUB 0x1e603800 macro
1662 FAIL_IF(push_inst(compiler, (FSUB ^ inv_bits) | VD(dst_r) | VN(src1) | VM(src2))); in sljit_emit_fop2()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 40 defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1321 VIR_A_ALU2(FSUB) in VIR_A_ALU2()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 415 (instregex "FSUB(S)?$"),
473 (instregex "FSUB(S)?_rec$"),
|