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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td27 def GPRMemAtomic : RegisterOperand<GPR> {
39 (outs GPR:$rd), (ins GPRMemAtomic:$rs1),
54 (outs GPR:$rd), (ins GPRMemAtomic:$rs1, GPR:$rs2),
65 def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
67 def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
68 (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
142 defm : AtomicStPat<atomic_store_8, SB, GPR>;
143 defm : AtomicStPat<atomic_store_16, SH, GPR>;
144 defm : AtomicStPat<atomic_store_32, SW, GPR>;
171 def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
[all …]
DRISCVInstrInfo.td300 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
309 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
318 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
323 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
329 : RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
330 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
336 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
341 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
346 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
352 : RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
[all …]
DRISCVInstrInfoM.td74 def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
75 (MULW GPR:$rs1, GPR:$rs2)>;
84 def : Pat<(zexti32 (riscv_divuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))),
85 (DIVU GPR:$rs1, GPR:$rs2)>;
86 def : Pat<(zexti32 (riscv_remuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))),
87 (REMU GPR:$rs1, GPR:$rs2)>;
92 def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)),
93 (REMW GPR:$rs1, GPR:$rs2)>;
94 def : Pat<(sext_inreg (srem (sexti32 GPR:$rs1),
95 (sexti32 GPR:$rs2)), i32),
[all …]
DRISCVInstrInfoF.td96 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
107 (ins GPR:$rs1, simm12:$imm12),
116 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
158 def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">,
162 def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
164 def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">,
168 def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
170 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
179 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
184 def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">,
[all …]
DRISCVInstrInfoD.td61 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
73 (ins GPR:$rs1, simm12:$imm12),
82 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
135 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
140 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
144 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
146 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
150 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
152 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
157 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
[all …]
DRISCVInstrFormats.td113 class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>
122 class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR>
123 … : Pseudo<(outs rdty:$rd, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
132 class PseudoStore<string opcodestr, RegisterClass rsty = GPR>
133 … : Pseudo<(outs rsty:$rs, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
DRISCVRegisterBanks.td13 def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td192 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
204 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td342 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
647 let MIOperandInfo = (ops GPR, i32imm);
658 let MIOperandInfo = (ops GPR, GPR, i32imm);
669 let MIOperandInfo = (ops GPR, i32imm);
975 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
996 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1052 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1053 // the GPR is purely vestigal at this point.
1074 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1099 let MIOperandInfo = (ops GPR, i32imm);
[all …]
DARMInstrVFP.td195 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
203 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
212 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
223 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
235 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
248 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
332 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
339 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
346 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
721 def : FP16Pat<(f16_to_fp GPR:$a),
[all …]
DARMInstrThumb2.td193 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
225 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
239 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
252 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
277 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
352 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
358 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
950 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
952 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
1433 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
[all …]
DARMRegisterInfo.td223 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
230 let AltOrders = [(add LR, GPR), (trunc GPR, 8),
231 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
241 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
253 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
266 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {
295 // restricted GPR register class. Many Thumb2 instructions allow the full
299 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
309 // the general GPR register class above (MOV, e.g.)
310 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
[all …]
DARMInstrThumb.td282 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
291 def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;
386 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
387 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
451 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
463 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
480 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
488 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
505 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
542 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
[all …]
DARMInstrNEON.td568 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
570 [(set DPair:$dst, (v2f64 (word_alignedload GPR:$Rn)))]>;
575 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
577 [(word_alignedstore (v2f64 DPair:$src), GPR:$Rn)]>;
584 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
588 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
592 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
599 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
603 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
607 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td80 let MIOperandInfo = (ops GPR, i16imm);
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
267 (outs GPR:$dst),
268 (ins GPR:$src2, GPR:$src),
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
272 (outs GPR:$dst),
273 (ins GPR:$src2, i64imm:$imm),
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
313 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenInstrInfo.inc14837 GPR = 308,
19279 OpTypes::GPR, OpTypes::GPR,
19280 OpTypes::GPR, OpTypes::GPR, OpTypes::mod_imm, OpTypes::i32imm, OpTypes::i32imm,
19281 OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm,
19282 OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::i32imm,
19283 …OpTypes::GPR, OpTypes::GPR, OpTypes::GPRnopc, OpTypes::GPRnopc, OpTypes::i32imm, OpTypes::i32imm, …
19286 OpTypes::GPR, OpTypes::GPR, OpTypes::imm0_32, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19289 OpTypes::i32imm, OpTypes::GPR, OpTypes::GPR, OpTypes::brtarget,
19290 OpTypes::i32imm, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::brtarget,
19294 OpTypes::GPR, OpTypes::GPR, OpTypes::i32imm,
[all …]
DARMGenDAGISel.inc87 …:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32…
88 // Dst: (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
125 …:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32…
126 // Dst: (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
761 …// Src: (or:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }), (imm:{ *:[i32] …
762 … // Dst: (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, (hi16:{ *:[i32] } (imm:{ *:[i32] }):$imm))
775 … // Src: (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, so_reg_reg:{ *:[i32] }:$shift) - Complexity = 15
776 // Dst: (ORRrsr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, so_reg_reg:{ *:[i32] }:$shift)
829 … // Src: (or:{ *:[i32] } so_reg_reg:{ *:[i32] }:$shift, GPR:{ *:[i32] }:$Rn) - Complexity = 15
830 // Dst: (ORRrsr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, so_reg_reg:{ *:[i32] }:$shift)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64GenRegisterBankInfo.def28 // 6: GPR 32-bit value.
30 // 7: GPR 64-bit value.
65 // 19: GPR 32-bit value.
69 // 22: GPR 64-bit value. <-- This must match Last3OpsIdx.
74 // 25: FPR 16-bit value to GPR 16-bit. <-- This must match
79 // 27: FPR 32-bit value to GPR 32-bit value.
82 // 29: FPR 64-bit value to GPR 64-bit value.
85 // 31: FPR 128-bit value to GPR 128-bit value (invalid)
88 // 33: FPR 256-bit value to GPR 256-bit value (invalid)
91 // 35: FPR 512-bit value to GPR 512-bit value (invalid)
[all …]
DAArch64RegisterBankInfo.cpp122 CHECK_VALUEMAP(GPR, 32); in AArch64RegisterBankInfo()
123 CHECK_VALUEMAP(GPR, 64); in AArch64RegisterBankInfo()
140 CHECK_VALUEMAP_3OPS(GPR, 32); in AArch64RegisterBankInfo()
141 CHECK_VALUEMAP_3OPS(GPR, 64); in AArch64RegisterBankInfo()
168 CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32); in AArch64RegisterBankInfo()
169 CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32); in AArch64RegisterBankInfo()
170 CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64); in AArch64RegisterBankInfo()
171 CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 64); in AArch64RegisterBankInfo()
173 CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 32); in AArch64RegisterBankInfo()
175 CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 64); in AArch64RegisterBankInfo()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceInstX8632.def32 // isGPR: This is a GPR (integer-type).
33 // is64: This is a 64-bit GPR.
34 // is32: This is a 32-bit GPR.
35 // is16: This is a 16-bit GPR.
36 // is8: This is an 8-bit GPR.
38 // is64To8: A 64-bit GPR truncable to 8-bit.
39 // is32To8: A 32-bit GPR truncable to 8-bit.
40 // is16To8: A 16-bit GPR truncable to 8-bit.
41 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
42 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
[all …]
DIceInstX8664.def41 // isGPR: This is a GPR (integer-type).
42 // is64: This is a 64-bit GPR.
43 // is32: This is a 32-bit GPR.
44 // is16: This is a 16-bit GPR.
45 // is8: This is an 8-bit GPR.
47 // is64To8: A 64-bit GPR truncable to 8-bit.
48 // is32To8: A 32-bit GPR truncable to 8-bit.
49 // is16To8: A 16-bit GPR truncable to 8-bit.
50 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
51 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DXmmArith.cpp1485 #define TestImplSXmmReg(Dst, GPR, Inst, Size, IntType) \ in TEST_F() argument
1488 "(" #Dst ", " #GPR ", cvt" #Inst ", " #IntType ", f" #Size ")"; \ in TEST_F()
1492 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##SrcValue)); \ in TEST_F()
1494 Encoded_GPR_##GPR()); \ in TEST_F()
1504 #define TestImplSRegXmm(GPR, Src, Inst, IntSize, Size) \ in TEST_F() argument
1507 "(" #GPR ", " #Src ", cvt" #Inst ", " #IntSize ", f" #Size ")"; \ in TEST_F()
1510 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##DstValue)); \ in TEST_F()
1512 __ cvt##Inst(IceType_i##IntSize, Encoded_GPR_##GPR(), IceType_f##Size, \ in TEST_F()
1520 test.GPR()) \ in TEST_F()
1564 #define TestImplSRegAddr(GPR, Inst, IntSize, Size) \ in TEST_F() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td28 // GPR - One of the 32 32-bit general-purpose registers
29 class GPR<bits<5> num, string n> : PPCReg<n> {
34 class GP8<GPR SubReg, string n> : PPCReg<n> {
41 class SPE<GPR SubReg, string n> : PPCReg<n> {
106 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
111 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
117 def S#Index : SPE<!cast<GPR>("R"#Index), "r"#Index>,
160 def ZERO : GPR<0, "0">, DwarfRegAlias<R0>;
164 def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
168 def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DXmmArith.cpp1412 #define TestImplSXmmReg(Dst, GPR, Inst, Size) \ in TEST_F() argument
1415 "(" #Dst ", " #GPR ", cvt" #Inst ", f" #Size ")"; \ in TEST_F()
1419 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \ in TEST_F()
1422 GPRRegister::Encoded_Reg_##GPR); \ in TEST_F()
1432 #define TestImplSRegXmm(GPR, Src, Inst, Size) \ in TEST_F() argument
1435 "(" #GPR ", " #Src ", cvt" #Inst ", f" #Size ")"; \ in TEST_F()
1438 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \ in TEST_F()
1441 __ cvt##Inst(IceType_i32, GPRRegister::Encoded_Reg_##GPR, IceType_f##Size, \ in TEST_F()
1448 ASSERT_EQ(static_cast<uint32_t>(Inst##Size##Expected), test.GPR()) \ in TEST_F()
1493 #define TestImplSRegAddr(GPR, Inst, Size) \ in TEST_F() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZMachineFunctionInfo.h69 void setVarArgsFirstGPR(unsigned GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR() argument

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