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Searched refs:ICIMVAU (Results 1 – 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
Dcachel1_armv7.h125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
Dcore_cm7.h496 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_cm33.h540 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_cm35p.h540 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_armv8mml.h540 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_armv81mml.h548 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_cm55.h548 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member