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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLiveRangeCalc.h102 LiveRange &LR; member
116 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill) in LiveInBlock()
117 : LR(LR), DomNode(node), Kill(kill) {} in LiveInBlock()
128 bool isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
148 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use,
172 void extendToUses(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask,
210 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
216 void createDeadDefs(LiveRange &LR, unsigned Reg);
222 void extendToUses(LiveRange &LR, unsigned PhysReg) { in extendToUses() argument
223 extendToUses(LR, PhysReg, LaneBitmask::getAll()); in extendToUses()
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DLiveIntervals.h184 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
187 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) { in extendToIndices() argument
188 extendToIndices(LR, Indices, /*Undefs=*/{}); in extendToIndices()
198 void pruneValue(LiveRange &LR, SlotIndex Kill,
245 bool isLiveInToMBB(const LiveRange &LR, in isLiveInToMBB() argument
247 return LR.liveAt(getMBBStartIdx(mbb)); in isLiveInToMBB()
250 bool isLiveOutOfMBB(const LiveRange &LR, in isLiveOutOfMBB() argument
252 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); in isLiveOutOfMBB()
394 LiveRange *LR = RegUnitRanges[Unit]; in getRegUnit() local
395 if (!LR) { in getRegUnit()
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DLiveIntervalUnion.h111 const LiveRange *LR = nullptr; variable
123 LR = &NewLR; in reset()
133 Query(const LiveRange &LR, const LiveIntervalUnion &LIU): in Query() argument
134 LiveUnion(&LIU), LR(&LR) {} in Query()
140 if (UserTag == NewUserTag && LR == &NewLR && LiveUnion == &NewLiveUnion && in init()
/third_party/libunwind/src/aarch64/
DGstash_frame.c44 rs->reg.where[LR], rs->reg.val[LR], DWARF_GET_LOC(d->loc[LR]), in tdep_stash_frame()
58 && rs->ret_addr_column == LR in tdep_stash_frame()
64 && (rs->reg.where[LR] == DWARF_WHERE_UNDEF in tdep_stash_frame()
65 || rs->reg.where[LR] == DWARF_WHERE_SAME in tdep_stash_frame()
66 || (rs->reg.where[LR] == DWARF_WHERE_CFAREL in tdep_stash_frame()
67 && labs(rs->reg.val[LR]) < (1 << 29) in tdep_stash_frame()
68 && rs->reg.val[LR]+1 != 0)) in tdep_stash_frame()
81 if (rs->reg.where[LR] == DWARF_WHERE_CFAREL) in tdep_stash_frame()
82 f->lr_cfa_offset = rs->reg.val[LR]; in tdep_stash_frame()
/third_party/libunwind/src/arm/
DGstash_frame.c44 rs->reg.where[LR], rs->reg.val[LR], DWARF_GET_LOC(d->loc[LR]), in tdep_stash_frame()
58 && rs->ret_addr_column == LR in tdep_stash_frame()
64 && (rs->reg.where[LR] == DWARF_WHERE_UNDEF in tdep_stash_frame()
65 || rs->reg.where[LR] == DWARF_WHERE_SAME in tdep_stash_frame()
66 || (rs->reg.where[LR] == DWARF_WHERE_CFAREL in tdep_stash_frame()
67 && labs(rs->reg.val[LR]) < (1 << 29) in tdep_stash_frame()
68 && rs->reg.val[LR]+1 != 0)) in tdep_stash_frame()
81 if (rs->reg.where[LR] == DWARF_WHERE_CFAREL) in tdep_stash_frame()
82 f->lr_cfa_offset = rs->reg.val[LR]; in tdep_stash_frame()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DLiveRangeUtils.h26 static void DistributeRange(LiveRangeT &LR, LiveRangeT *SplitLRs[], in DistributeRange() argument
29 typename LiveRangeT::iterator J = LR.begin(), E = LR.end(); in DistributeRange()
40 LR.segments.erase(J, E); in DistributeRange()
43 unsigned j = 0, e = LR.getNumValNums(); in DistributeRange()
47 VNInfo *VNI = LR.getValNumInfo(i); in DistributeRange()
53 LR.valnos[j++] = VNI; in DistributeRange()
56 LR.valnos.resize(j); in DistributeRange()
DRegAllocFast.cpp192 void killVirtReg(LiveReg &LR);
194 void spillVirtReg(MachineBasicBlock::iterator MI, LiveReg &LR);
211 void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint);
369 void RegAllocFast::addKillFlag(const LiveReg &LR) { in addKillFlag() argument
370 if (!LR.LastUse) return; in addKillFlag()
371 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); in addKillFlag()
372 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
373 if (MO.getReg() == LR.PhysReg) in addKillFlag()
388 void RegAllocFast::killVirtReg(LiveReg &LR) { in killVirtReg() argument
389 addKillFlag(LR); in killVirtReg()
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DLiveRangeCalc.cpp65 LiveRange &LR, const MachineOperand &MO) { in createDeadDef() argument
71 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
147 void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { in createDeadDefs() argument
153 createDeadDef(*Indexes, *Alloc, LR, MO); in createDeadDefs()
156 void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, LaneBitmask Mask, in extendToUses() argument
212 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
235 Updater.setDest(&I.LR); in updateFromLiveIns()
241 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, in extend() argument
251 auto EP = LR.extendInBlock(Undefs, Indexes->getMBBStartIdx(UseMBB), Use); in extend()
259 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs)) in extend()
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DLiveInterval.cpp67 LiveRange *LR; member in __anon752681f30111::CalcLiveRangeUtilBase
70 CalcLiveRangeUtilBase(LiveRange *LR) : LR(LR) {} in CalcLiveRangeUtilBase() argument
94 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
115 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
142 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
145 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
147 if (LR->isUndefIn(Undefs, I->end, BeforeUse)) in extendInBlock()
288 CalcLiveRangeUtilVector(LiveRange *LR) : CalcLiveRangeUtilVectorBase(LR) {} in CalcLiveRangeUtilVector() argument
293 LiveRange::Segments &segmentsColl() { return LR->segments; } in segmentsColl()
295 void insertAtEnd(const Segment &S) { LR->segments.push_back(S); } in insertAtEnd()
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DLiveIntervals.cpp117 for (LiveRange *LR : RegUnitRanges) in releaseMemory()
118 delete LR; in releaseMemory()
159 if (LiveRange *LR = RegUnitRanges[Unit]) in print() local
160 OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n'; in print()
268 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { in computeRegUnitRange() argument
284 LRCalc->createDeadDefs(LR, Reg); in computeRegUnitRange()
303 LRCalc->extendToUses(LR, Reg); in computeRegUnitRange()
310 LR.flushSegmentSet(); in computeRegUnitRange()
335 LiveRange *LR = RegUnitRanges[Unit]; in computeLiveInRegUnits() local
336 if (!LR) { in computeLiveInRegUnits()
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DLiveRegMatrix.cpp178 LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR, in query() argument
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
200 [&](unsigned Unit, const LiveRange &LR) { in checkInterference() argument
201 return query(LR, Unit).checkInterference(); in checkInterference()
214 LiveRange LR; in checkInterference() local
215 LR.addSegment(Seg); in checkInterference()
219 if (query(LR, *Units).checkInterference()) in checkInterference()
DMachineVerifier.cpp251 void report_context(const LiveRange &LR, unsigned VRegUnit,
257 void report_context_liverange(const LiveRange &LR) const;
266 SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
269 SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
527 void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit, in report_context() argument
529 report_context_liverange(LR); in report_context()
543 void MachineVerifier::report_context_liverange(const LiveRange &LR) const { in report_context_liverange()
544 errs() << "- liverange: " << LR << '\n'; in report_context_liverange()
1870 unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit, in checkLivenessAtUse() argument
1872 LiveQueryResult LRQ = LR.Query(UseIdx); in checkLivenessAtUse()
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DRegisterCoalescer.cpp1484 if (LiveRange *LR = LIS->getCachedRegUnit(*Units)) in reMaterializeTrivialDef() local
1485 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
1499 if (LiveRange *LR = LIS->getCachedRegUnit(*Units)) in reMaterializeTrivialDef() local
1500 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
2115 LiveRange &LR = LIS->getRegUnit(*UI); in joinReservedPhysReg() local
2116 LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator()); in joinReservedPhysReg()
2200 LiveRange &LR; member in __anon880f23740311::JoinVals
2373 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
2377 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
2380 TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums()) {} in JoinVals()
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DLiveIntervalUnion.cpp128 if (LR->empty() || LiveUnion->empty()) { in collectInterferingVRegs()
134 LRI = LR->begin(); in collectInterferingVRegs()
139 LiveRange::const_iterator LREnd = LR->end(); in collectInterferingVRegs()
166 LRI = LR->advanceTo(LRI, LiveUnionI.start()); in collectInterferingVRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/GSYM/
DFunctionInfo.cpp155 LookupResult LR; in lookup() local
156 LR.LookupAddr = Addr; in lookup()
157 LR.FuncRange.Start = FuncAddr; in lookup()
159 LR.FuncRange.End = FuncAddr + Data.getU32(&Offset); in lookup()
170 if (Addr >= LR.FuncRange.End) in lookup()
178 LR.FuncName = GR.getString(NameOffset); in lookup()
222 SrcLoc.Name = LR.FuncName; in lookup()
223 LR.Locations.push_back(SrcLoc); in lookup()
224 return LR; in lookup()
234 SrcLoc.Name = LR.FuncName; in lookup()
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DLookupResult.cpp54 raw_ostream &llvm::gsym::operator<<(raw_ostream &OS, const LookupResult &LR) { in operator <<() argument
55 OS << HEX64(LR.LookupAddr) << ": "; in operator <<()
56 auto NumLocations = LR.Locations.size(); in operator <<()
63 OS << LR.Locations[I]; in operator <<()
/third_party/ffmpeg/libavutil/
Dtwofish.c26 #define LR(x, n) ((x) << (n) | (x) >> (32 - (n))) macro
216 t1 = MDS_mul(cs, LR(P[1], 8)); in twofish_encrypt()
218 P[3] = LR(P[3], 1) ^ (t0 + 2 * t1 + cs->K[2 * i + 9]); in twofish_encrypt()
220 t1 = MDS_mul(cs, LR(P[3], 8)); in twofish_encrypt()
222 P[1] = LR(P[1], 1) ^ (t0 + 2 * t1 + cs->K[2 * i + 11]); in twofish_encrypt()
244 t1 = MDS_mul(cs, LR(P[3], 8)); in twofish_decrypt()
245 P[0] = LR(P[0], 1) ^ (t0 + t1 + cs->K[2 * i + 8]); in twofish_decrypt()
248 t1 = MDS_mul(cs, LR(P[1], 8)); in twofish_decrypt()
249 P[2] = LR(P[2], 1) ^ (t0 + t1 + cs->K[2 * i + 6]); in twofish_decrypt()
301 B = LR(B, 8); in av_twofish_init()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ExecutionEngine/Orc/
DLambdaResolver.h65 using LR = LambdaResolver<DylibLookupFtorT, ExternalLookupFtorT>; in createLambdaResolver() local
66 return std::make_unique<LR>(std::move(DylibLookupFtor), in createLambdaResolver()
75 using LR = LambdaResolver<DylibLookupFtorT, ExternalLookupFtorT>; in createLambdaResolver() local
76 return std::make_unique<LR>(AcknowledgeORCv1Deprecation, in createLambdaResolver()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td266 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
271 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
281 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
293 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
299 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
304 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
308 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
317 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
328 // For most interrupts, all registers except SP and LR are shared with
329 // user-space. We mark LR to be saved anyway, since this is what the ARM backend
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DThumb1FrameLowering.cpp223 case ARM::LR: in emitPrologue()
288 case ARM::LR: in emitPrologue()
464 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) && in isCSRestore()
574 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
691 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
728 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
781 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in spillCalleeSavedRegisters()
831 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in spillCalleeSavedRegisters()
837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters()
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DARMFrameLowering.cpp437 case ARM::LR: in emitPrologue()
644 case ARM::LR: in emitPrologue()
1088 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && in emitPopInst()
1136 Regs[0] = ARM::LR; in emitPopInst()
1676 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1682 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1729 if (Reg == ARM::LR) in determineCalleeSaves()
1737 case ARM::LR: in determineCalleeSaves()
1760 case ARM::LR: in determineCalleeSaves()
1880 SavedRegs.set(ARM::LR); in determineCalleeSaves()
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DARMRegisterInfo.td94 def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>;
224 SP, LR, PC)> {
225 // Allocate LR as the first CSR since it is always saved anyway.
230 let AltOrders = [(add LR, GPR), (trunc GPR, 8),
231 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
242 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8),
243 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
254 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
262 def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
267 let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)];
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/third_party/libinput/doc/user/
Darchitecture.rst39 rankdir="LR";
65 rankdir="LR";
108 rankdir="LR";
160 rankdir="LR";
190 rankdir="LR";
236 rankdir="LR";
261 rankdir="LR";
297 rankdir="LR";
/third_party/musl/src/crypt/
Dcrypt_blowfish.c700 BF_word L, LR[2]; in BF_crypt() local
703 LR[1] = BF_magic_w[i + 1]; in BF_crypt()
707 L = BF_encrypt(&data.ctx, L, LR[1], in BF_crypt()
708 &LR[0], &LR[0]); in BF_crypt()
712 data.binary.output[i + 1] = LR[1]; in BF_crypt()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td364 // requires the frame-record (LR, FP) to be at the top the callee-save area,
367 // FIXME: LR is only callee-saved in the sense that *we* preserve it and are
369 // is currently safe since BL has LR as an implicit-def and what happens after a
374 // end up saving LR as part of a call frame). Watch this space...
376 X25, X26, X27, X28, LR, FP,
381 def CSR_Darwin_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
386 // Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.
387 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
388 // and not (LR,FP) pairs.
390 X25, X26, X27, X28, FP, LR,
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