| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 121 Register NewVR = MRI->createVirtualRegister(RC); in InsertNewDef() local
122 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR); in InsertNewDef()
225 unsigned NewVR = 0; in RewriteUse() local
228 NewVR = GetValueAtEndOfBlockInternal(SourceBB); in RewriteUse()
230 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
233 U.setReg(NewVR); in RewriteUse()
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| D | PeepholeOptimizer.cpp | 585 Register NewVR = MRI->createVirtualRegister(RC); in INITIALIZE_PASS_DEPENDENCY() local
587 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
594 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
765 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI() local
768 TII.get(TargetOpcode::PHI), NewVR); in insertPHI()
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| D | TargetInstrInfo.cpp | 829 Register NewVR = MRI.createVirtualRegister(RC); in reassociateOps() local
830 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in reassociateOps()
839 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR) in reassociateOps()
845 .addReg(NewVR, getKillRegState(true)); in reassociateOps()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 4247 Register NewVR = MRI.createVirtualRegister(RC); in genNeg() local
4249 BuildMI(MF, Root.getDebugLoc(), TII->get(MnegOpc), NewVR) in genNeg()
4254 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in genNeg()
4256 return NewVR; in genNeg()
4268 Register NewVR = in genFusedMultiplyAccNeg() local
4271 FMAInstKind::Accumulator, &NewVR); in genFusedMultiplyAccNeg()
4295 Register NewVR = in genFusedMultiplyIdxNeg() local
4299 FMAInstKind::Indexed, &NewVR); in genFusedMultiplyIdxNeg()
4430 Register NewVR = MRI.createVirtualRegister(OrrRC); in genAlternativeCodeSequence() local
4441 BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR) in genAlternativeCodeSequence()
[all …]
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| D | AArch64ISelLowering.cpp | 13327 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
13337 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
13344 .addReg(NewVR); in insertCopiesSplitCSR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 1407 Register NewVR = MRI->createVirtualRegister(RC); in generateInserts() local
1408 RegMap[VR] = NewVR; in generateInserts()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 2013 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
2016 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
2023 .addReg(NewVR); in insertCopiesSplitCSR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 15378 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
15388 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
15395 .addReg(NewVR); in insertCopiesSplitCSR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 17464 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
17474 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
17481 .addReg(NewVR); in insertCopiesSplitCSR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 47253 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
47263 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
47270 .addReg(NewVR); in insertCopiesSplitCSR()
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