Searched refs:OP_BFIND (Results 1 – 11 of 11) sorted by relevance
| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_target_gm107.cpp | 143 case OP_BFIND: in isBarrierRequired()
257 case OP_BFIND: in getLatency()
284 case OP_BFIND: in getReadLatency()
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| D | nv50_ir_target_nvc0.cpp | 139 { OP_BFIND, 0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
498 case OP_BFIND: in isModSupported()
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| D | nv50_ir_target_gv100.cpp | 239 case OP_BFIND: return &opInfo_FLO; in getOpInfo()
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| D | nv50_ir.h | 156 OP_BFIND, // find highest/lowest set bit enumerator
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| D | nv50_ir_from_nir.cpp | 388 return OP_BFIND; in getOperation()
1949 mkOp1(OP_BFIND, TYPE_U32, tmp, tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT; in visit()
2784 mkOp1(OP_BFIND, TYPE_U32, newDefs[0], tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT; in visit()
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| D | nv50_ir_from_tgsi.cpp | 3466 mkOp1(OP_BFIND, TYPE_U32, val0, val0)->subOp = NV50_IR_SUBOP_BFIND_SAMT; in handleInstruction()
3888 geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], val0); in handleInstruction()
3896 mkOp1(OP_BFIND, srcTy, dst0[c], src0); in handleInstruction()
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| D | nv50_ir_emit_gv100.cpp | 1793 case OP_BFIND: in emitInstruction()
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| D | nv50_ir_emit_gk110.cpp | 2709 case OP_BFIND: in emitInstruction()
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| D | nv50_ir_emit_nvc0.cpp | 2903 case OP_BFIND: in emitInstruction()
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| D | nv50_ir_emit_gm107.cpp | 3575 case OP_BFIND: in emitInstruction()
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| D | nv50_ir_peephole.cpp | 1559 case OP_BFIND: { in opnd()
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