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Searched refs:PKT3 (Results 1 – 25 of 41) sorted by relevance

12

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_reg_shadowing.c59 si_pm4_cmd_add(pm4, PKT3(packet, 1 + num_ranges * 2, 0)); in si_build_load_reg()
81 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
86 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
90 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
97 si_pm4_cmd_add(pm4, PKT3(PKT3_RELEASE_MEM, 6, 0)); in si_create_shadowing_ib_preamble()
114 si_pm4_cmd_add(pm4, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in si_create_shadowing_ib_preamble()
131 si_pm4_cmd_add(pm4, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in si_create_shadowing_ib_preamble()
140 si_pm4_cmd_add(pm4, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_create_shadowing_ib_preamble()
149 si_pm4_cmd_add(pm4, PKT3(PKT3_ACQUIRE_MEM, 5, 0)); in si_create_shadowing_ib_preamble()
157 si_pm4_cmd_add(pm4, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_create_shadowing_ib_preamble()
[all …]
Dsi_gfx_cs.c121 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_gfx_cs()
571 radeon_emit(PKT3(PKT3_NOP, 0, 0)); in si_trace_emit()
593 radeon_emit(PKT3(PKT3_ACQUIRE_MEM, 5, 0)); in si_emit_surface_sync()
602 radeon_emit(PKT3(PKT3_SURFACE_SYNC, 3, 0)); in si_emit_surface_sync()
662 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_emit_cache_flush()
705 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_emit_cache_flush()
712 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_emit_cache_flush()
735 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_emit_cache_flush()
741 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_emit_cache_flush()
748 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_emit_cache_flush()
[all …]
Dsi_build_pm4.h79 radeon_emit(PKT3(PKT3_SET_CONFIG_REG, num, 0)); \
91 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
108 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
116 radeon_emit(PKT3(PKT3_SET_SH_REG, num, 0)); \
123 radeon_emit(PKT3(PKT3_SET_SH_REG_INDEX, num, 0)); \
140 radeon_emit(PKT3(PKT3_SET_UCONFIG_REG, num, perfctr)); \
162 radeon_emit(PKT3(__opcode, 1, 0)); \
287 radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); \
Dsi_state_streamout.c225 radeon_emit(PKT3(PKT3_WRITE_DATA, 3, 0)); in si_flush_vgt_streamout()
238 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_vgt_streamout()
241 radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_flush_vgt_streamout()
277 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0)); in si_emit_streamout_begin()
301 radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_begin()
313 radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_begin()
349 radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_end()
Dsi_sqtt.c223 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_thread_trace_start()
270 radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); in si_copy_thread_trace_info_regs()
298 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_thread_trace_stop()
302 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_thread_trace_stop()
329 radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_emit_thread_trace_stop()
343 radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_emit_thread_trace_stop()
356 radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_emit_thread_trace_stop()
387 radeon_emit(PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_thread_trace_start()
392 radeon_emit(PKT3(PKT3_NOP, 0, 0)); in si_thread_trace_start()
441 radeon_emit(PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_thread_trace_stop()
[all …]
Dsi_cp_dma.c104 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0)); in si_emit_cp_dma()
114 radeon_emit(PKT3(PKT3_CP_DMA, 4, 0)); in si_emit_cp_dma()
128 radeon_emit(PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_emit_cp_dma()
462 radeon_emit(PKT3(PKT3_WRITE_DATA, 2 + size / 4, 0)); in si_cp_write_data()
486 radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); in si_cp_copy_data()
Dsi_fence.c111 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cp_release_mem()
120 radeon_emit(PKT3(PKT3_RELEASE_MEM, ctx->gfx_level >= GFX9 ? 6 : 5, 0)); in si_cp_release_mem()
138 radeon_emit(PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); in si_cp_release_mem()
149 radeon_emit(PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); in si_cp_release_mem()
178 radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_cp_wait_mem()
Dsi_perfcounter.c135 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_start()
153 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
157 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
179 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_spm_start()
193 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_spm_stop()
235 radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); in si_pc_emit_read()
248 radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); in si_pc_emit_read()
863 radeon_emit(PKT3(PKT3_WRITE_DATA, 2 + AC_SPM_MUXSEL_LINE_SIZE, 0)); in si_emit_spm_setup()
Dsi_state_draw.cpp442 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0)); in si_cp_dma_prefetch_inline()
1425 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); \
1513 radeon_emit(PKT3(PKT3_INDEX_TYPE, 0, 0)); in si_emit_draw_packets()
1560 radeon_emit(PKT3(PKT3_SET_BASE, 2, 0)); in si_emit_draw_packets()
1573 radeon_emit(PKT3(PKT3_INDEX_BASE, 1, 0)); in si_emit_draw_packets()
1577 radeon_emit(PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); in si_emit_draw_packets()
1582 radeon_emit(PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT : PKT3_DRAW_INDIRECT, 3, in si_emit_draw_packets()
1600 radeon_emit(PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI : PKT3_DRAW_INDIRECT_MULTI, 8, in si_emit_draw_packets()
1619 radeon_emit(PKT3(PKT3_NUM_INSTANCES, 0, 0)); in si_emit_draw_packets()
1702 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit)); in si_emit_draw_packets()
[all …]
Dsi_query.c799 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_sample_streamout()
819 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_query_hw_do_emit_start()
827 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_query_hw_do_emit_start()
874 radeon_emit(PKT3(PKT3_WRITE_DATA, 2 + 1, 0)); in si_query_hw_do_emit_start()
884 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_query_hw_do_emit_start()
938 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_query_hw_do_emit_stop()
977 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_query_hw_do_emit_stop()
985 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_query_hw_do_emit_stop()
1045 radeon_emit(PKT3(PKT3_SET_PREDICATION, 2, 0)); in emit_set_predicate()
1050 radeon_emit(PKT3(PKT3_SET_PREDICATION, 1, 0)); in emit_set_predicate()
/third_party/mesa3d/src/amd/vulkan/
Dradv_cs.h48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
65 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
81 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
91 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0)); in radeon_set_context_reg_rmw()
103 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
126 radeon_emit(cs, PKT3(opcode, 1, 0)); in radeon_set_sh_reg_idx()
137 radeon_emit(cs, PKT3(PKT3_SET_SH_REG_INDEX, 1, 0)); in gfx10_set_sh_reg_idx3()
148 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
158 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1)); in radeon_set_uconfig_reg_seq_perfctr()
182 radeon_emit(cs, PKT3(opcode, 1, 0)); in radeon_set_uconfig_reg_idx()
[all …]
Dsi_cmd_buffer.c204 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_emit_graphics()
209 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0)); in si_emit_graphics()
949 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cs_emit_write_event_eop()
955 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false)); in si_cs_emit_write_event_eop()
975 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, false)); in si_cs_emit_write_event_eop()
983 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, false)); in si_cs_emit_write_event_eop()
995 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
1003 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
1019 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false)); in radv_cp_wait_mem()
1033 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec)); in si_emit_acquire_mem()
[all …]
Dradv_sqtt.c201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_start()
245 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_copy_thread_trace_info_regs()
265 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_stop()
269 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_stop()
289 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_emit_thread_trace_stop()
305 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_emit_thread_trace_stop()
318 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_emit_thread_trace_stop()
549 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in radv_begin_thread_trace()
554 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in radv_begin_thread_trace()
618 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in radv_end_thread_trace()
[all …]
Dradv_perfcounter.c45 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_windowed_counters()
526 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_pc_emit_block_instance_read()
562 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_pc_wait_idle()
565 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in radv_pc_wait_idle()
574 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in radv_pc_wait_idle()
585 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_pc_stop_and_sample()
602 radeon_emit(cs, PKT3(PKT3_COND_EXEC, 3, 0)); in radv_pc_stop_and_sample()
632 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); in radv_pc_stop_and_sample()
666 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); in radv_pc_begin_query()
685 radeon_emit(cs, PKT3(PKT3_COND_EXEC, 3, 0)); in radv_pc_begin_query()
Dradv_cmd_buffer.c383 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); in radv_emit_write_data_packet()
692 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in radv_cmd_buffer_trace_emit()
851 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cmd_buffer_after_draw()
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_batch_break_on_new_ps()
2143 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0)); in radv_update_zrange_precision()
2312 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating)); in radv_set_ds_clear_metadata()
2335 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating)); in radv_set_ds_clear_metadata()
2360 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating)); in radv_set_tc_compat_zrange_metadata()
2445 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0)); in radv_load_ds_clear_metadata()
2451 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_load_ds_clear_metadata()
[all …]
Dradv_device_generated_commands.c269 nir_ssa_def *values[2] = {nir_imm_int(b, PKT3(PKT3_NUM_INSTANCES, 0, false)), instance_count}; in dgc_emit_instance_count()
278 nir_ssa_def *values[5] = {nir_imm_int(b, PKT3(PKT3_DRAW_INDEX_OFFSET_2, 3, false)), in dgc_emit_draw_indexed()
288 nir_ssa_def *values[3] = {nir_imm_int(b, PKT3(PKT3_DRAW_INDEX_AUTO, 1, false)), vertex_count, in dgc_emit_draw()
559 nir_imm_int(&b, PKT3(PKT3_SET_SH_REG, 1, 0)), load_param16(&b, vbo_reg), in build_dgc_prepare_shader()
653 nir_imm_int(&b, PKT3(PKT3_SET_SH_REG, 1, 0)), in build_dgc_prepare_shader()
742 nir_imm_int(&b, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)), in build_dgc_prepare_shader()
838 cmd_values[0] = nir_imm_int(&b, PKT3(opcode, 1, 0)); in build_dgc_prepare_shader()
843 cmd_values[0] = nir_imm_int(&b, PKT3(PKT3_INDEX_TYPE, 0, 0)); in build_dgc_prepare_shader()
851 cmd_values[3] = nir_imm_int(&b, PKT3(PKT3_INDEX_BASE, 1, 0)); in build_dgc_prepare_shader()
854 cmd_values[6] = nir_imm_int(&b, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); in build_dgc_prepare_shader()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h123 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
132 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
146 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
162 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
171 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
185 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
201 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); in radeon_set_uconfig_reg_idx()
Dr600_hw_context.c125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
238 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); in r600_flush_emit()
246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
250 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
442 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in r600_emit_pfp_sync_me()
469 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0)); in r600_emit_pfp_sync_me()
[all …]
Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_vgt_streamout()
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in r600_flush_vgt_streamout()
212 radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0)); in r600_emit_streamout_begin()
225 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_begin()
237 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_begin()
248 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_streamout_begin()
268 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_end()
Devergreen_state.c1763 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ in evergreen_emit_image_state()
1766 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ in evergreen_emit_image_state()
1769 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */ in evergreen_emit_image_state()
1772 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */ in evergreen_emit_image_state()
1780 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/ in evergreen_emit_image_state()
1783 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); in evergreen_emit_image_state()
1787 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
1790 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); in evergreen_emit_image_state()
1794 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
1798 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
[all …]
Devergreen_hw_context.c129 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in evergreen_cp_dma_clear_buffer()
136 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in evergreen_cp_dma_clear_buffer()
Dr600_state.c1394 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1407 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1444 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_framebuffer_state()
1467 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1479 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_framebuffer_state()
1563 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_db_state()
1682 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); in r600_emit_vertex_buffers()
1694 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_vertex_buffers()
1726 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_constant_buffers()
[all …]
Dr600_pipe.h884 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT… macro
907 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); in r600_store_config_reg_seq()
919 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; in r600_store_context_reg_seq()
931 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; in r600_store_ctl_const_seq()
939 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); in r600_store_loop_const_seq()
951 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; in eg_store_loop_const_seq()
999 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0)); in radeon_set_ctl_const_seq()
Dr600_state_common.c1783 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_setup_scratch_area_for_shader()
1801 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_setup_scratch_area_for_shader()
1819 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_setup_scratch_area_for_shader()
2411 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); in r600_draw_vbo()
2421 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0)); in r600_draw_vbo()
2426 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_draw_vbo()
2434 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); in r600_draw_vbo()
2442 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit)); in r600_draw_vbo()
2450 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit)); in r600_draw_vbo()
2455 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_draw_vbo()
[all …]
/third_party/mesa3d/src/amd/common/
Dsid.h275 #define PKT3(op, count, predicate) \ macro
279 #define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */

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