1 /* libunwind - a platform-independent unwind library 2 Copyright (C) 2003-2004 Hewlett-Packard Co 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> 4 Copyright (C) 2013 Linaro Limited 5 6 This file is part of libunwind. 7 8 Permission is hereby granted, free of charge, to any person obtaining 9 a copy of this software and associated documentation files (the 10 "Software"), to deal in the Software without restriction, including 11 without limitation the rights to use, copy, modify, merge, publish, 12 distribute, sublicense, and/or sell copies of the Software, and to 13 permit persons to whom the Software is furnished to do so, subject to 14 the following conditions: 15 16 The above copyright notice and this permission notice shall be 17 included in all copies or substantial portions of the Software. 18 19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE 23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 26 27 #include "_UPT_internal.h" 28 29 #include <stddef.h> 30 31 #ifdef HAVE_ASM_PTRACE_H 32 # include <asm/ptrace.h> 33 #endif 34 35 #ifdef HAVE_ASM_PTRACE_OFFSETS_H 36 # include <asm/ptrace_offsets.h> 37 #endif 38 39 #if defined(__powerpc64__) && defined(__FreeBSD__) 40 #define PT_R0 0 41 #define PT_R1 1 42 #define PT_R2 2 43 #define PT_R3 3 44 #define PT_R4 4 45 #define PT_R5 5 46 #define PT_R6 6 47 #define PT_R7 7 48 #define PT_R8 8 49 #define PT_R9 9 50 #define PT_R10 10 51 #define PT_R11 11 52 #define PT_R12 12 53 #define PT_R13 13 54 #define PT_R14 14 55 #define PT_R15 15 56 #define PT_R16 16 57 #define PT_R17 17 58 #define PT_R18 18 59 #define PT_R19 19 60 #define PT_R20 20 61 #define PT_R21 21 62 #define PT_R22 22 63 #define PT_R23 23 64 #define PT_R24 24 65 #define PT_R25 25 66 #define PT_R26 26 67 #define PT_R27 27 68 #define PT_R28 28 69 #define PT_R29 29 70 #define PT_R30 30 71 #define PT_R31 31 72 #define PT_NIP 32 73 #define PT_CTR 35 74 #define PT_LNK 36 75 #define PT_XER 37 76 #define PT_FPR0 48 77 #define PT_VR0 82 78 #define PT_VSCR (PT_VR0 + 32*2 + 1) 79 #define PT_VRSAVE (PT_VR0 + 33*2) 80 #endif 81 82 const int _UPT_reg_offset[UNW_REG_LAST + 1] = 83 { 84 #ifdef HAVE_ASM_PTRACE_OFFSETS_H 85 # ifndef PT_AR_CSD 86 # define PT_AR_CSD -1 /* this was introduced with rev 2.1 of ia64 */ 87 # endif 88 89 [UNW_IA64_GR + 0] = -1, [UNW_IA64_GR + 1] = PT_R1, 90 [UNW_IA64_GR + 2] = PT_R2, [UNW_IA64_GR + 3] = PT_R3, 91 [UNW_IA64_GR + 4] = PT_R4, [UNW_IA64_GR + 5] = PT_R5, 92 [UNW_IA64_GR + 6] = PT_R6, [UNW_IA64_GR + 7] = PT_R7, 93 [UNW_IA64_GR + 8] = PT_R8, [UNW_IA64_GR + 9] = PT_R9, 94 [UNW_IA64_GR + 10] = PT_R10, [UNW_IA64_GR + 11] = PT_R11, 95 [UNW_IA64_GR + 12] = PT_R12, [UNW_IA64_GR + 13] = PT_R13, 96 [UNW_IA64_GR + 14] = PT_R14, [UNW_IA64_GR + 15] = PT_R15, 97 [UNW_IA64_GR + 16] = PT_R16, [UNW_IA64_GR + 17] = PT_R17, 98 [UNW_IA64_GR + 18] = PT_R18, [UNW_IA64_GR + 19] = PT_R19, 99 [UNW_IA64_GR + 20] = PT_R20, [UNW_IA64_GR + 21] = PT_R21, 100 [UNW_IA64_GR + 22] = PT_R22, [UNW_IA64_GR + 23] = PT_R23, 101 [UNW_IA64_GR + 24] = PT_R24, [UNW_IA64_GR + 25] = PT_R25, 102 [UNW_IA64_GR + 26] = PT_R26, [UNW_IA64_GR + 27] = PT_R27, 103 [UNW_IA64_GR + 28] = PT_R28, [UNW_IA64_GR + 29] = PT_R29, 104 [UNW_IA64_GR + 30] = PT_R30, [UNW_IA64_GR + 31] = PT_R31, 105 106 [UNW_IA64_NAT+ 0] = -1, [UNW_IA64_NAT+ 1] = PT_NAT_BITS, 107 [UNW_IA64_NAT+ 2] = PT_NAT_BITS, [UNW_IA64_NAT+ 3] = PT_NAT_BITS, 108 [UNW_IA64_NAT+ 4] = PT_NAT_BITS, [UNW_IA64_NAT+ 5] = PT_NAT_BITS, 109 [UNW_IA64_NAT+ 6] = PT_NAT_BITS, [UNW_IA64_NAT+ 7] = PT_NAT_BITS, 110 [UNW_IA64_NAT+ 8] = PT_NAT_BITS, [UNW_IA64_NAT+ 9] = PT_NAT_BITS, 111 [UNW_IA64_NAT+ 10] = PT_NAT_BITS, [UNW_IA64_NAT+ 11] = PT_NAT_BITS, 112 [UNW_IA64_NAT+ 12] = PT_NAT_BITS, [UNW_IA64_NAT+ 13] = PT_NAT_BITS, 113 [UNW_IA64_NAT+ 14] = PT_NAT_BITS, [UNW_IA64_NAT+ 15] = PT_NAT_BITS, 114 [UNW_IA64_NAT+ 16] = PT_NAT_BITS, [UNW_IA64_NAT+ 17] = PT_NAT_BITS, 115 [UNW_IA64_NAT+ 18] = PT_NAT_BITS, [UNW_IA64_NAT+ 19] = PT_NAT_BITS, 116 [UNW_IA64_NAT+ 20] = PT_NAT_BITS, [UNW_IA64_NAT+ 21] = PT_NAT_BITS, 117 [UNW_IA64_NAT+ 22] = PT_NAT_BITS, [UNW_IA64_NAT+ 23] = PT_NAT_BITS, 118 [UNW_IA64_NAT+ 24] = PT_NAT_BITS, [UNW_IA64_NAT+ 25] = PT_NAT_BITS, 119 [UNW_IA64_NAT+ 26] = PT_NAT_BITS, [UNW_IA64_NAT+ 27] = PT_NAT_BITS, 120 [UNW_IA64_NAT+ 28] = PT_NAT_BITS, [UNW_IA64_NAT+ 29] = PT_NAT_BITS, 121 [UNW_IA64_NAT+ 30] = PT_NAT_BITS, [UNW_IA64_NAT+ 31] = PT_NAT_BITS, 122 123 [UNW_IA64_FR + 0] = -1, [UNW_IA64_FR + 1] = -1, 124 [UNW_IA64_FR + 2] = PT_F2, [UNW_IA64_FR + 3] = PT_F3, 125 [UNW_IA64_FR + 4] = PT_F4, [UNW_IA64_FR + 5] = PT_F5, 126 [UNW_IA64_FR + 6] = PT_F6, [UNW_IA64_FR + 7] = PT_F7, 127 [UNW_IA64_FR + 8] = PT_F8, [UNW_IA64_FR + 9] = PT_F9, 128 [UNW_IA64_FR + 10] = PT_F10, [UNW_IA64_FR + 11] = PT_F11, 129 [UNW_IA64_FR + 12] = PT_F12, [UNW_IA64_FR + 13] = PT_F13, 130 [UNW_IA64_FR + 14] = PT_F14, [UNW_IA64_FR + 15] = PT_F15, 131 [UNW_IA64_FR + 16] = PT_F16, [UNW_IA64_FR + 17] = PT_F17, 132 [UNW_IA64_FR + 18] = PT_F18, [UNW_IA64_FR + 19] = PT_F19, 133 [UNW_IA64_FR + 20] = PT_F20, [UNW_IA64_FR + 21] = PT_F21, 134 [UNW_IA64_FR + 22] = PT_F22, [UNW_IA64_FR + 23] = PT_F23, 135 [UNW_IA64_FR + 24] = PT_F24, [UNW_IA64_FR + 25] = PT_F25, 136 [UNW_IA64_FR + 26] = PT_F26, [UNW_IA64_FR + 27] = PT_F27, 137 [UNW_IA64_FR + 28] = PT_F28, [UNW_IA64_FR + 29] = PT_F29, 138 [UNW_IA64_FR + 30] = PT_F30, [UNW_IA64_FR + 31] = PT_F31, 139 [UNW_IA64_FR + 32] = PT_F32, [UNW_IA64_FR + 33] = PT_F33, 140 [UNW_IA64_FR + 34] = PT_F34, [UNW_IA64_FR + 35] = PT_F35, 141 [UNW_IA64_FR + 36] = PT_F36, [UNW_IA64_FR + 37] = PT_F37, 142 [UNW_IA64_FR + 38] = PT_F38, [UNW_IA64_FR + 39] = PT_F39, 143 [UNW_IA64_FR + 40] = PT_F40, [UNW_IA64_FR + 41] = PT_F41, 144 [UNW_IA64_FR + 42] = PT_F42, [UNW_IA64_FR + 43] = PT_F43, 145 [UNW_IA64_FR + 44] = PT_F44, [UNW_IA64_FR + 45] = PT_F45, 146 [UNW_IA64_FR + 46] = PT_F46, [UNW_IA64_FR + 47] = PT_F47, 147 [UNW_IA64_FR + 48] = PT_F48, [UNW_IA64_FR + 49] = PT_F49, 148 [UNW_IA64_FR + 50] = PT_F50, [UNW_IA64_FR + 51] = PT_F51, 149 [UNW_IA64_FR + 52] = PT_F52, [UNW_IA64_FR + 53] = PT_F53, 150 [UNW_IA64_FR + 54] = PT_F54, [UNW_IA64_FR + 55] = PT_F55, 151 [UNW_IA64_FR + 56] = PT_F56, [UNW_IA64_FR + 57] = PT_F57, 152 [UNW_IA64_FR + 58] = PT_F58, [UNW_IA64_FR + 59] = PT_F59, 153 [UNW_IA64_FR + 60] = PT_F60, [UNW_IA64_FR + 61] = PT_F61, 154 [UNW_IA64_FR + 62] = PT_F62, [UNW_IA64_FR + 63] = PT_F63, 155 [UNW_IA64_FR + 64] = PT_F64, [UNW_IA64_FR + 65] = PT_F65, 156 [UNW_IA64_FR + 66] = PT_F66, [UNW_IA64_FR + 67] = PT_F67, 157 [UNW_IA64_FR + 68] = PT_F68, [UNW_IA64_FR + 69] = PT_F69, 158 [UNW_IA64_FR + 70] = PT_F70, [UNW_IA64_FR + 71] = PT_F71, 159 [UNW_IA64_FR + 72] = PT_F72, [UNW_IA64_FR + 73] = PT_F73, 160 [UNW_IA64_FR + 74] = PT_F74, [UNW_IA64_FR + 75] = PT_F75, 161 [UNW_IA64_FR + 76] = PT_F76, [UNW_IA64_FR + 77] = PT_F77, 162 [UNW_IA64_FR + 78] = PT_F78, [UNW_IA64_FR + 79] = PT_F79, 163 [UNW_IA64_FR + 80] = PT_F80, [UNW_IA64_FR + 81] = PT_F81, 164 [UNW_IA64_FR + 82] = PT_F82, [UNW_IA64_FR + 83] = PT_F83, 165 [UNW_IA64_FR + 84] = PT_F84, [UNW_IA64_FR + 85] = PT_F85, 166 [UNW_IA64_FR + 86] = PT_F86, [UNW_IA64_FR + 87] = PT_F87, 167 [UNW_IA64_FR + 88] = PT_F88, [UNW_IA64_FR + 89] = PT_F89, 168 [UNW_IA64_FR + 90] = PT_F90, [UNW_IA64_FR + 91] = PT_F91, 169 [UNW_IA64_FR + 92] = PT_F92, [UNW_IA64_FR + 93] = PT_F93, 170 [UNW_IA64_FR + 94] = PT_F94, [UNW_IA64_FR + 95] = PT_F95, 171 [UNW_IA64_FR + 96] = PT_F96, [UNW_IA64_FR + 97] = PT_F97, 172 [UNW_IA64_FR + 98] = PT_F98, [UNW_IA64_FR + 99] = PT_F99, 173 [UNW_IA64_FR +100] = PT_F100, [UNW_IA64_FR +101] = PT_F101, 174 [UNW_IA64_FR +102] = PT_F102, [UNW_IA64_FR +103] = PT_F103, 175 [UNW_IA64_FR +104] = PT_F104, [UNW_IA64_FR +105] = PT_F105, 176 [UNW_IA64_FR +106] = PT_F106, [UNW_IA64_FR +107] = PT_F107, 177 [UNW_IA64_FR +108] = PT_F108, [UNW_IA64_FR +109] = PT_F109, 178 [UNW_IA64_FR +110] = PT_F110, [UNW_IA64_FR +111] = PT_F111, 179 [UNW_IA64_FR +112] = PT_F112, [UNW_IA64_FR +113] = PT_F113, 180 [UNW_IA64_FR +114] = PT_F114, [UNW_IA64_FR +115] = PT_F115, 181 [UNW_IA64_FR +116] = PT_F116, [UNW_IA64_FR +117] = PT_F117, 182 [UNW_IA64_FR +118] = PT_F118, [UNW_IA64_FR +119] = PT_F119, 183 [UNW_IA64_FR +120] = PT_F120, [UNW_IA64_FR +121] = PT_F121, 184 [UNW_IA64_FR +122] = PT_F122, [UNW_IA64_FR +123] = PT_F123, 185 [UNW_IA64_FR +124] = PT_F124, [UNW_IA64_FR +125] = PT_F125, 186 [UNW_IA64_FR +126] = PT_F126, [UNW_IA64_FR +127] = PT_F127, 187 188 [UNW_IA64_AR + 0] = -1, [UNW_IA64_AR + 1] = -1, 189 [UNW_IA64_AR + 2] = -1, [UNW_IA64_AR + 3] = -1, 190 [UNW_IA64_AR + 4] = -1, [UNW_IA64_AR + 5] = -1, 191 [UNW_IA64_AR + 6] = -1, [UNW_IA64_AR + 7] = -1, 192 [UNW_IA64_AR + 8] = -1, [UNW_IA64_AR + 9] = -1, 193 [UNW_IA64_AR + 10] = -1, [UNW_IA64_AR + 11] = -1, 194 [UNW_IA64_AR + 12] = -1, [UNW_IA64_AR + 13] = -1, 195 [UNW_IA64_AR + 14] = -1, [UNW_IA64_AR + 15] = -1, 196 [UNW_IA64_AR + 16] = PT_AR_RSC, [UNW_IA64_AR + 17] = PT_AR_BSP, 197 [UNW_IA64_AR + 18] = PT_AR_BSPSTORE,[UNW_IA64_AR + 19] = PT_AR_RNAT, 198 [UNW_IA64_AR + 20] = -1, [UNW_IA64_AR + 21] = -1, 199 [UNW_IA64_AR + 22] = -1, [UNW_IA64_AR + 23] = -1, 200 [UNW_IA64_AR + 24] = -1, [UNW_IA64_AR + 25] = PT_AR_CSD, 201 [UNW_IA64_AR + 26] = -1, [UNW_IA64_AR + 27] = -1, 202 [UNW_IA64_AR + 28] = -1, [UNW_IA64_AR + 29] = -1, 203 [UNW_IA64_AR + 30] = -1, [UNW_IA64_AR + 31] = -1, 204 [UNW_IA64_AR + 32] = PT_AR_CCV, [UNW_IA64_AR + 33] = -1, 205 [UNW_IA64_AR + 34] = -1, [UNW_IA64_AR + 35] = -1, 206 [UNW_IA64_AR + 36] = PT_AR_UNAT, [UNW_IA64_AR + 37] = -1, 207 [UNW_IA64_AR + 38] = -1, [UNW_IA64_AR + 39] = -1, 208 [UNW_IA64_AR + 40] = PT_AR_FPSR, [UNW_IA64_AR + 41] = -1, 209 [UNW_IA64_AR + 42] = -1, [UNW_IA64_AR + 43] = -1, 210 [UNW_IA64_AR + 44] = -1, [UNW_IA64_AR + 45] = -1, 211 [UNW_IA64_AR + 46] = -1, [UNW_IA64_AR + 47] = -1, 212 [UNW_IA64_AR + 48] = -1, [UNW_IA64_AR + 49] = -1, 213 [UNW_IA64_AR + 50] = -1, [UNW_IA64_AR + 51] = -1, 214 [UNW_IA64_AR + 52] = -1, [UNW_IA64_AR + 53] = -1, 215 [UNW_IA64_AR + 54] = -1, [UNW_IA64_AR + 55] = -1, 216 [UNW_IA64_AR + 56] = -1, [UNW_IA64_AR + 57] = -1, 217 [UNW_IA64_AR + 58] = -1, [UNW_IA64_AR + 59] = -1, 218 [UNW_IA64_AR + 60] = -1, [UNW_IA64_AR + 61] = -1, 219 [UNW_IA64_AR + 62] = -1, [UNW_IA64_AR + 63] = -1, 220 [UNW_IA64_AR + 64] = PT_AR_PFS, [UNW_IA64_AR + 65] = PT_AR_LC, 221 [UNW_IA64_AR + 66] = PT_AR_EC, [UNW_IA64_AR + 67] = -1, 222 [UNW_IA64_AR + 68] = -1, [UNW_IA64_AR + 69] = -1, 223 [UNW_IA64_AR + 70] = -1, [UNW_IA64_AR + 71] = -1, 224 [UNW_IA64_AR + 72] = -1, [UNW_IA64_AR + 73] = -1, 225 [UNW_IA64_AR + 74] = -1, [UNW_IA64_AR + 75] = -1, 226 [UNW_IA64_AR + 76] = -1, [UNW_IA64_AR + 77] = -1, 227 [UNW_IA64_AR + 78] = -1, [UNW_IA64_AR + 79] = -1, 228 [UNW_IA64_AR + 80] = -1, [UNW_IA64_AR + 81] = -1, 229 [UNW_IA64_AR + 82] = -1, [UNW_IA64_AR + 83] = -1, 230 [UNW_IA64_AR + 84] = -1, [UNW_IA64_AR + 85] = -1, 231 [UNW_IA64_AR + 86] = -1, [UNW_IA64_AR + 87] = -1, 232 [UNW_IA64_AR + 88] = -1, [UNW_IA64_AR + 89] = -1, 233 [UNW_IA64_AR + 90] = -1, [UNW_IA64_AR + 91] = -1, 234 [UNW_IA64_AR + 92] = -1, [UNW_IA64_AR + 93] = -1, 235 [UNW_IA64_AR + 94] = -1, [UNW_IA64_AR + 95] = -1, 236 [UNW_IA64_AR + 96] = -1, [UNW_IA64_AR + 97] = -1, 237 [UNW_IA64_AR + 98] = -1, [UNW_IA64_AR + 99] = -1, 238 [UNW_IA64_AR +100] = -1, [UNW_IA64_AR +101] = -1, 239 [UNW_IA64_AR +102] = -1, [UNW_IA64_AR +103] = -1, 240 [UNW_IA64_AR +104] = -1, [UNW_IA64_AR +105] = -1, 241 [UNW_IA64_AR +106] = -1, [UNW_IA64_AR +107] = -1, 242 [UNW_IA64_AR +108] = -1, [UNW_IA64_AR +109] = -1, 243 [UNW_IA64_AR +110] = -1, [UNW_IA64_AR +111] = -1, 244 [UNW_IA64_AR +112] = -1, [UNW_IA64_AR +113] = -1, 245 [UNW_IA64_AR +114] = -1, [UNW_IA64_AR +115] = -1, 246 [UNW_IA64_AR +116] = -1, [UNW_IA64_AR +117] = -1, 247 [UNW_IA64_AR +118] = -1, [UNW_IA64_AR +119] = -1, 248 [UNW_IA64_AR +120] = -1, [UNW_IA64_AR +121] = -1, 249 [UNW_IA64_AR +122] = -1, [UNW_IA64_AR +123] = -1, 250 [UNW_IA64_AR +124] = -1, [UNW_IA64_AR +125] = -1, 251 [UNW_IA64_AR +126] = -1, [UNW_IA64_AR +127] = -1, 252 253 [UNW_IA64_BR + 0] = PT_B0, [UNW_IA64_BR + 1] = PT_B1, 254 [UNW_IA64_BR + 2] = PT_B2, [UNW_IA64_BR + 3] = PT_B3, 255 [UNW_IA64_BR + 4] = PT_B4, [UNW_IA64_BR + 5] = PT_B5, 256 [UNW_IA64_BR + 6] = PT_B6, [UNW_IA64_BR + 7] = PT_B7, 257 258 [UNW_IA64_PR] = PT_PR, 259 [UNW_IA64_CFM] = PT_CFM, 260 [UNW_IA64_IP] = PT_CR_IIP 261 #elif defined(HAVE_TTRACE) 262 # warning No support for ttrace() yet. 263 #elif defined(UNW_TARGET_HPPA) 264 [UNW_HPPA_GR + 0] = 0x000, [UNW_HPPA_GR + 1] = 0x004, 265 [UNW_HPPA_GR + 2] = 0x008, [UNW_HPPA_GR + 3] = 0x00c, 266 [UNW_HPPA_GR + 4] = 0x010, [UNW_HPPA_GR + 5] = 0x014, 267 [UNW_HPPA_GR + 6] = 0x018, [UNW_HPPA_GR + 7] = 0x01c, 268 [UNW_HPPA_GR + 8] = 0x020, [UNW_HPPA_GR + 9] = 0x024, 269 [UNW_HPPA_GR + 10] = 0x028, [UNW_HPPA_GR + 11] = 0x02c, 270 [UNW_HPPA_GR + 12] = 0x030, [UNW_HPPA_GR + 13] = 0x034, 271 [UNW_HPPA_GR + 14] = 0x038, [UNW_HPPA_GR + 15] = 0x03c, 272 [UNW_HPPA_GR + 16] = 0x040, [UNW_HPPA_GR + 17] = 0x044, 273 [UNW_HPPA_GR + 18] = 0x048, [UNW_HPPA_GR + 19] = 0x04c, 274 [UNW_HPPA_GR + 20] = 0x050, [UNW_HPPA_GR + 21] = 0x054, 275 [UNW_HPPA_GR + 22] = 0x058, [UNW_HPPA_GR + 23] = 0x05c, 276 [UNW_HPPA_GR + 24] = 0x060, [UNW_HPPA_GR + 25] = 0x064, 277 [UNW_HPPA_GR + 26] = 0x068, [UNW_HPPA_GR + 27] = 0x06c, 278 [UNW_HPPA_GR + 28] = 0x070, [UNW_HPPA_GR + 29] = 0x074, 279 [UNW_HPPA_GR + 30] = 0x078, [UNW_HPPA_GR + 31] = 0x07c, 280 281 [UNW_HPPA_FR + 0] = 0x080, [UNW_HPPA_FR + 1] = 0x088, 282 [UNW_HPPA_FR + 2] = 0x090, [UNW_HPPA_FR + 3] = 0x098, 283 [UNW_HPPA_FR + 4] = 0x0a0, [UNW_HPPA_FR + 5] = 0x0a8, 284 [UNW_HPPA_FR + 6] = 0x0b0, [UNW_HPPA_FR + 7] = 0x0b8, 285 [UNW_HPPA_FR + 8] = 0x0c0, [UNW_HPPA_FR + 9] = 0x0c8, 286 [UNW_HPPA_FR + 10] = 0x0d0, [UNW_HPPA_FR + 11] = 0x0d8, 287 [UNW_HPPA_FR + 12] = 0x0e0, [UNW_HPPA_FR + 13] = 0x0e8, 288 [UNW_HPPA_FR + 14] = 0x0f0, [UNW_HPPA_FR + 15] = 0x0f8, 289 [UNW_HPPA_FR + 16] = 0x100, [UNW_HPPA_FR + 17] = 0x108, 290 [UNW_HPPA_FR + 18] = 0x110, [UNW_HPPA_FR + 19] = 0x118, 291 [UNW_HPPA_FR + 20] = 0x120, [UNW_HPPA_FR + 21] = 0x128, 292 [UNW_HPPA_FR + 22] = 0x130, [UNW_HPPA_FR + 23] = 0x138, 293 [UNW_HPPA_FR + 24] = 0x140, [UNW_HPPA_FR + 25] = 0x148, 294 [UNW_HPPA_FR + 26] = 0x150, [UNW_HPPA_FR + 27] = 0x158, 295 [UNW_HPPA_FR + 28] = 0x160, [UNW_HPPA_FR + 29] = 0x168, 296 [UNW_HPPA_FR + 30] = 0x170, [UNW_HPPA_FR + 31] = 0x178, 297 298 [UNW_HPPA_IP] = 0x1a8 /* IAOQ[0] */ 299 #elif defined(UNW_TARGET_X86) 300 #if defined __FreeBSD__ 301 #define UNW_R_OFF(R, r) \ 302 [UNW_X86_##R] = offsetof(gregset_t, r_##r), 303 UNW_R_OFF(EAX, eax) 304 UNW_R_OFF(EDX, edx) 305 UNW_R_OFF(ECX, ecx) 306 UNW_R_OFF(EBX, ebx) 307 UNW_R_OFF(ESI, esi) 308 UNW_R_OFF(EDI, edi) 309 UNW_R_OFF(EBP, ebp) 310 UNW_R_OFF(ESP, esp) 311 UNW_R_OFF(EIP, eip) 312 // UNW_R_OFF(CS, cs) 313 // UNW_R_OFF(EFLAGS, eflags) 314 // UNW_R_OFF(SS, ss) 315 #elif defined __linux__ 316 [UNW_X86_EAX] = 0x18, 317 [UNW_X86_EBX] = 0x00, 318 [UNW_X86_ECX] = 0x04, 319 [UNW_X86_EDX] = 0x08, 320 [UNW_X86_ESI] = 0x0c, 321 [UNW_X86_EDI] = 0x10, 322 [UNW_X86_EBP] = 0x14, 323 [UNW_X86_EIP] = 0x30, 324 [UNW_X86_ESP] = 0x3c 325 /* CS = 0x34, */ 326 /* DS = 0x1c, */ 327 /* ES = 0x20, */ 328 /* FS = 0x24, */ 329 /* GS = 0x28, */ 330 /* ORIG_EAX = 0x2c, */ 331 /* EFLAGS = 0x38, */ 332 /* SS = 0x40 */ 333 #else 334 #error Port me 335 #endif 336 #elif defined(UNW_TARGET_X86_64) 337 #if defined __FreeBSD__ 338 #define UNW_R_OFF(R, r) \ 339 [UNW_X86_64_##R] = offsetof(gregset_t, r_##r), 340 UNW_R_OFF(RAX, rax) 341 UNW_R_OFF(RDX, rdx) 342 UNW_R_OFF(RCX, rcx) 343 UNW_R_OFF(RBX, rbx) 344 UNW_R_OFF(RSI, rsi) 345 UNW_R_OFF(RDI, rdi) 346 UNW_R_OFF(RBP, rbp) 347 UNW_R_OFF(RSP, rsp) 348 UNW_R_OFF(R8, r8) 349 UNW_R_OFF(R9, r9) 350 UNW_R_OFF(R10, r10) 351 UNW_R_OFF(R11, r11) 352 UNW_R_OFF(R12, r12) 353 UNW_R_OFF(R13, r13) 354 UNW_R_OFF(R14, r14) 355 UNW_R_OFF(R15, r15) 356 UNW_R_OFF(RIP, rip) 357 // UNW_R_OFF(CS, cs) 358 // UNW_R_OFF(EFLAGS, rflags) 359 // UNW_R_OFF(SS, ss) 360 #undef UNW_R_OFF 361 #elif defined __linux__ 362 [UNW_X86_64_RAX] = 0x50, 363 [UNW_X86_64_RDX] = 0x60, 364 [UNW_X86_64_RCX] = 0x58, 365 [UNW_X86_64_RBX] = 0x28, 366 [UNW_X86_64_RSI] = 0x68, 367 [UNW_X86_64_RDI] = 0x70, 368 [UNW_X86_64_RBP] = 0x20, 369 [UNW_X86_64_RSP] = 0x98, 370 [UNW_X86_64_R8] = 0x48, 371 [UNW_X86_64_R9] = 0x40, 372 [UNW_X86_64_R10] = 0x38, 373 [UNW_X86_64_R11] = 0x30, 374 [UNW_X86_64_R12] = 0x18, 375 [UNW_X86_64_R13] = 0x10, 376 [UNW_X86_64_R14] = 0x08, 377 [UNW_X86_64_R15] = 0x00, 378 [UNW_X86_64_RIP] = 0x80 379 // [UNW_X86_64_CS] = 0x88, 380 // [UNW_X86_64_EFLAGS] = 0x90, 381 // [UNW_X86_64_RSP] = 0x98, 382 // [UNW_X86_64_SS] = 0xa0 383 #else 384 #error Port me 385 #endif 386 #elif defined(UNW_TARGET_PPC32) || defined(UNW_TARGET_PPC64) 387 388 #define UNW_REG_SLOT_SIZE sizeof(unsigned long) 389 #define UNW_PPC_R(v) ((v) * UNW_REG_SLOT_SIZE) 390 #define UNW_PPC_PT(p) UNW_PPC_R(PT_##p) 391 392 #define UNW_FP_OFF(b, i) \ 393 [UNW_PPC##b##_F##i] = UNW_PPC_R(PT_FPR0 + i * 8/UNW_REG_SLOT_SIZE) 394 395 #define UNW_R_OFF(b, i) \ 396 [UNW_PPC##b##_R##i] = UNW_PPC_R(PT_R##i) 397 398 #define UNW_PPC_REGS(b) \ 399 UNW_R_OFF(b, 0), \ 400 UNW_R_OFF(b, 1), \ 401 UNW_R_OFF(b, 2), \ 402 UNW_R_OFF(b, 3), \ 403 UNW_R_OFF(b, 4), \ 404 UNW_R_OFF(b, 5), \ 405 UNW_R_OFF(b, 6), \ 406 UNW_R_OFF(b, 7), \ 407 UNW_R_OFF(b, 8), \ 408 UNW_R_OFF(b, 9), \ 409 UNW_R_OFF(b, 10), \ 410 UNW_R_OFF(b, 11), \ 411 UNW_R_OFF(b, 12), \ 412 UNW_R_OFF(b, 13), \ 413 UNW_R_OFF(b, 14), \ 414 UNW_R_OFF(b, 15), \ 415 UNW_R_OFF(b, 16), \ 416 UNW_R_OFF(b, 17), \ 417 UNW_R_OFF(b, 18), \ 418 UNW_R_OFF(b, 19), \ 419 UNW_R_OFF(b, 20), \ 420 UNW_R_OFF(b, 21), \ 421 UNW_R_OFF(b, 22), \ 422 UNW_R_OFF(b, 23), \ 423 UNW_R_OFF(b, 24), \ 424 UNW_R_OFF(b, 25), \ 425 UNW_R_OFF(b, 26), \ 426 UNW_R_OFF(b, 27), \ 427 UNW_R_OFF(b, 28), \ 428 UNW_R_OFF(b, 29), \ 429 UNW_R_OFF(b, 30), \ 430 UNW_R_OFF(b, 31), \ 431 \ 432 [UNW_PPC##b##_CTR] = UNW_PPC_PT(CTR), \ 433 [UNW_PPC##b##_XER] = UNW_PPC_PT(XER), \ 434 [UNW_PPC##b##_LR] = UNW_PPC_PT(LNK), \ 435 \ 436 UNW_FP_OFF(b, 0), \ 437 UNW_FP_OFF(b, 1), \ 438 UNW_FP_OFF(b, 2), \ 439 UNW_FP_OFF(b, 3), \ 440 UNW_FP_OFF(b, 4), \ 441 UNW_FP_OFF(b, 5), \ 442 UNW_FP_OFF(b, 6), \ 443 UNW_FP_OFF(b, 7), \ 444 UNW_FP_OFF(b, 8), \ 445 UNW_FP_OFF(b, 9), \ 446 UNW_FP_OFF(b, 10), \ 447 UNW_FP_OFF(b, 11), \ 448 UNW_FP_OFF(b, 12), \ 449 UNW_FP_OFF(b, 13), \ 450 UNW_FP_OFF(b, 14), \ 451 UNW_FP_OFF(b, 15), \ 452 UNW_FP_OFF(b, 16), \ 453 UNW_FP_OFF(b, 17), \ 454 UNW_FP_OFF(b, 18), \ 455 UNW_FP_OFF(b, 19), \ 456 UNW_FP_OFF(b, 20), \ 457 UNW_FP_OFF(b, 21), \ 458 UNW_FP_OFF(b, 22), \ 459 UNW_FP_OFF(b, 23), \ 460 UNW_FP_OFF(b, 24), \ 461 UNW_FP_OFF(b, 25), \ 462 UNW_FP_OFF(b, 26), \ 463 UNW_FP_OFF(b, 27), \ 464 UNW_FP_OFF(b, 28), \ 465 UNW_FP_OFF(b, 29), \ 466 UNW_FP_OFF(b, 30), \ 467 UNW_FP_OFF(b, 31) 468 469 #define UNW_PPC32_REGS \ 470 [UNW_PPC32_FPSCR] = UNW_PPC_PT(FPSCR), \ 471 [UNW_PPC32_CCR] = UNW_PPC_PT(CCR) 472 473 #define UNW_VR_OFF(i) \ 474 [UNW_PPC64_V##i] = UNW_PPC_R(PT_VR0 + i * 2) 475 476 #define UNW_PPC64_REGS \ 477 [UNW_PPC64_NIP] = UNW_PPC_PT(NIP), \ 478 [UNW_PPC64_FRAME_POINTER] = -1, \ 479 [UNW_PPC64_ARG_POINTER] = -1, \ 480 [UNW_PPC64_CR0] = -1, \ 481 [UNW_PPC64_CR1] = -1, \ 482 [UNW_PPC64_CR2] = -1, \ 483 [UNW_PPC64_CR3] = -1, \ 484 [UNW_PPC64_CR4] = -1, \ 485 [UNW_PPC64_CR5] = -1, \ 486 [UNW_PPC64_CR6] = -1, \ 487 [UNW_PPC64_CR7] = -1, \ 488 [UNW_PPC64_VRSAVE] = UNW_PPC_PT(VRSAVE), \ 489 [UNW_PPC64_VSCR] = UNW_PPC_PT(VSCR), \ 490 [UNW_PPC64_SPE_ACC] = -1, \ 491 [UNW_PPC64_SPEFSCR] = -1, \ 492 UNW_VR_OFF(0), \ 493 UNW_VR_OFF(1), \ 494 UNW_VR_OFF(2), \ 495 UNW_VR_OFF(3), \ 496 UNW_VR_OFF(4), \ 497 UNW_VR_OFF(5), \ 498 UNW_VR_OFF(6), \ 499 UNW_VR_OFF(7), \ 500 UNW_VR_OFF(8), \ 501 UNW_VR_OFF(9), \ 502 UNW_VR_OFF(10), \ 503 UNW_VR_OFF(11), \ 504 UNW_VR_OFF(12), \ 505 UNW_VR_OFF(13), \ 506 UNW_VR_OFF(14), \ 507 UNW_VR_OFF(15), \ 508 UNW_VR_OFF(16), \ 509 UNW_VR_OFF(17), \ 510 UNW_VR_OFF(18), \ 511 UNW_VR_OFF(19), \ 512 UNW_VR_OFF(20), \ 513 UNW_VR_OFF(21), \ 514 UNW_VR_OFF(22), \ 515 UNW_VR_OFF(23), \ 516 UNW_VR_OFF(24), \ 517 UNW_VR_OFF(25), \ 518 UNW_VR_OFF(26), \ 519 UNW_VR_OFF(27), \ 520 UNW_VR_OFF(28), \ 521 UNW_VR_OFF(29), \ 522 UNW_VR_OFF(30), \ 523 UNW_VR_OFF(31) 524 525 #if defined(UNW_TARGET_PPC32) 526 UNW_PPC_REGS(32), 527 UNW_PPC32_REGS, 528 #else 529 UNW_PPC_REGS(64), 530 UNW_PPC64_REGS, 531 #endif 532 533 #elif defined(UNW_TARGET_ARM) 534 #if defined(__linux__) || defined(__FreeBSD__) 535 [UNW_ARM_R0] = 0x00, 536 [UNW_ARM_R1] = 0x04, 537 [UNW_ARM_R2] = 0x08, 538 [UNW_ARM_R3] = 0x0c, 539 [UNW_ARM_R4] = 0x10, 540 [UNW_ARM_R5] = 0x14, 541 [UNW_ARM_R6] = 0x18, 542 [UNW_ARM_R7] = 0x1c, 543 [UNW_ARM_R8] = 0x20, 544 [UNW_ARM_R9] = 0x24, 545 [UNW_ARM_R10] = 0x28, 546 [UNW_ARM_R11] = 0x2c, 547 [UNW_ARM_R12] = 0x30, 548 [UNW_ARM_R13] = 0x34, 549 [UNW_ARM_R14] = 0x38, 550 [UNW_ARM_R15] = 0x3c, 551 #else 552 #error Fix me 553 #endif 554 #elif defined(UNW_TARGET_MIPS) 555 [UNW_MIPS_R0] = 0, 556 [UNW_MIPS_R1] = 1, 557 [UNW_MIPS_R2] = 2, 558 [UNW_MIPS_R3] = 3, 559 [UNW_MIPS_R4] = 4, 560 [UNW_MIPS_R5] = 5, 561 [UNW_MIPS_R6] = 6, 562 [UNW_MIPS_R7] = 7, 563 [UNW_MIPS_R8] = 8, 564 [UNW_MIPS_R9] = 9, 565 [UNW_MIPS_R10] = 10, 566 [UNW_MIPS_R11] = 11, 567 [UNW_MIPS_R12] = 12, 568 [UNW_MIPS_R13] = 13, 569 [UNW_MIPS_R14] = 14, 570 [UNW_MIPS_R15] = 15, 571 [UNW_MIPS_R16] = 16, 572 [UNW_MIPS_R17] = 17, 573 [UNW_MIPS_R18] = 18, 574 [UNW_MIPS_R19] = 19, 575 [UNW_MIPS_R20] = 20, 576 [UNW_MIPS_R21] = 21, 577 [UNW_MIPS_R22] = 22, 578 [UNW_MIPS_R23] = 23, 579 [UNW_MIPS_R24] = 24, 580 [UNW_MIPS_R25] = 25, 581 [UNW_MIPS_R26] = 26, 582 [UNW_MIPS_R27] = 27, 583 [UNW_MIPS_R28] = 28, 584 [UNW_MIPS_R29] = 29, 585 [UNW_MIPS_R30] = 30, 586 [UNW_MIPS_R31] = 31, 587 [UNW_MIPS_PC] = 64, 588 #elif defined(UNW_TARGET_SH) 589 #elif defined(UNW_TARGET_AARCH64) 590 [UNW_AARCH64_X0] = 0x00, 591 [UNW_AARCH64_X1] = 0x08, 592 [UNW_AARCH64_X2] = 0x10, 593 [UNW_AARCH64_X3] = 0x18, 594 [UNW_AARCH64_X4] = 0x20, 595 [UNW_AARCH64_X5] = 0x28, 596 [UNW_AARCH64_X6] = 0x30, 597 [UNW_AARCH64_X7] = 0x38, 598 [UNW_AARCH64_X8] = 0x40, 599 [UNW_AARCH64_X9] = 0x48, 600 [UNW_AARCH64_X10] = 0x50, 601 [UNW_AARCH64_X11] = 0x58, 602 [UNW_AARCH64_X12] = 0x60, 603 [UNW_AARCH64_X13] = 0x68, 604 [UNW_AARCH64_X14] = 0x70, 605 [UNW_AARCH64_X15] = 0x78, 606 [UNW_AARCH64_X16] = 0x80, 607 [UNW_AARCH64_X17] = 0x88, 608 [UNW_AARCH64_X18] = 0x90, 609 [UNW_AARCH64_X19] = 0x98, 610 [UNW_AARCH64_X20] = 0xa0, 611 [UNW_AARCH64_X21] = 0xa8, 612 [UNW_AARCH64_X22] = 0xb0, 613 [UNW_AARCH64_X23] = 0xb8, 614 [UNW_AARCH64_X24] = 0xc0, 615 [UNW_AARCH64_X25] = 0xc8, 616 [UNW_AARCH64_X26] = 0xd0, 617 [UNW_AARCH64_X27] = 0xd8, 618 [UNW_AARCH64_X28] = 0xe0, 619 [UNW_AARCH64_X29] = 0xe8, 620 [UNW_AARCH64_X30] = 0xf0, 621 [UNW_AARCH64_SP] = 0xf8, 622 [UNW_AARCH64_PC] = 0x100, 623 [UNW_AARCH64_PSTATE] = 0x108 624 #elif defined(UNW_TARGET_TILEGX) 625 [UNW_TILEGX_R0] = 0x00, 626 [UNW_TILEGX_R1] = 0x08, 627 [UNW_TILEGX_R2] = 0x10, 628 [UNW_TILEGX_R3] = 0x08, 629 [UNW_TILEGX_R4] = 0x20, 630 [UNW_TILEGX_R5] = 0x28, 631 [UNW_TILEGX_R6] = 0x30, 632 [UNW_TILEGX_R7] = 0x38, 633 [UNW_TILEGX_R8] = 0x40, 634 [UNW_TILEGX_R9] = 0x48, 635 [UNW_TILEGX_R10] = 0x50, 636 [UNW_TILEGX_R11] = 0x58, 637 [UNW_TILEGX_R12] = 0x60, 638 [UNW_TILEGX_R13] = 0x68, 639 [UNW_TILEGX_R14] = 0x70, 640 [UNW_TILEGX_R15] = 0x78, 641 [UNW_TILEGX_R16] = 0x80, 642 [UNW_TILEGX_R17] = 0x88, 643 [UNW_TILEGX_R18] = 0x90, 644 [UNW_TILEGX_R19] = 0x98, 645 [UNW_TILEGX_R20] = 0xa0, 646 [UNW_TILEGX_R21] = 0xa8, 647 [UNW_TILEGX_R22] = 0xb0, 648 [UNW_TILEGX_R23] = 0xb8, 649 [UNW_TILEGX_R24] = 0xc0, 650 [UNW_TILEGX_R25] = 0xc8, 651 [UNW_TILEGX_R26] = 0xd0, 652 [UNW_TILEGX_R27] = 0xd8, 653 [UNW_TILEGX_R28] = 0xe0, 654 [UNW_TILEGX_R29] = 0xe8, 655 [UNW_TILEGX_R30] = 0xf0, 656 [UNW_TILEGX_R31] = 0xf8, 657 [UNW_TILEGX_R32] = 0x100, 658 [UNW_TILEGX_R33] = 0x108, 659 [UNW_TILEGX_R34] = 0x110, 660 [UNW_TILEGX_R35] = 0x118, 661 [UNW_TILEGX_R36] = 0x120, 662 [UNW_TILEGX_R37] = 0x128, 663 [UNW_TILEGX_R38] = 0x130, 664 [UNW_TILEGX_R39] = 0x138, 665 [UNW_TILEGX_R40] = 0x140, 666 [UNW_TILEGX_R41] = 0x148, 667 [UNW_TILEGX_R42] = 0x150, 668 [UNW_TILEGX_R43] = 0x158, 669 [UNW_TILEGX_R44] = 0x160, 670 [UNW_TILEGX_R45] = 0x168, 671 [UNW_TILEGX_R46] = 0x170, 672 [UNW_TILEGX_R47] = 0x178, 673 [UNW_TILEGX_R48] = 0x180, 674 [UNW_TILEGX_R49] = 0x188, 675 [UNW_TILEGX_R50] = 0x190, 676 [UNW_TILEGX_R51] = 0x198, 677 [UNW_TILEGX_R52] = 0x1a0, 678 [UNW_TILEGX_R53] = 0x1a8, 679 [UNW_TILEGX_R54] = 0x1b0, 680 [UNW_TILEGX_R55] = 0x1b8, 681 [UNW_TILEGX_PC] = 0x1a0 682 #elif defined(UNW_TARGET_S390X) 683 [UNW_S390X_R0] = 0x10, 684 [UNW_S390X_R1] = 0x18, 685 [UNW_S390X_R2] = 0x20, 686 [UNW_S390X_R3] = 0x28, 687 [UNW_S390X_R4] = 0x30, 688 [UNW_S390X_R5] = 0x38, 689 [UNW_S390X_R6] = 0x40, 690 [UNW_S390X_R7] = 0x48, 691 [UNW_S390X_R8] = 0x50, 692 [UNW_S390X_R9] = 0x58, 693 [UNW_S390X_R10] = 0x60, 694 [UNW_S390X_R11] = 0x68, 695 [UNW_S390X_R12] = 0x70, 696 [UNW_S390X_R13] = 0x78, 697 [UNW_S390X_R14] = 0x80, 698 [UNW_S390X_R15] = 0x88, 699 [UNW_S390X_F0] = 0xe0, 700 [UNW_S390X_F1] = 0xe8, 701 [UNW_S390X_F2] = 0xf0, 702 [UNW_S390X_F3] = 0xf8, 703 [UNW_S390X_F4] = 0x100, 704 [UNW_S390X_F5] = 0x108, 705 [UNW_S390X_F6] = 0x110, 706 [UNW_S390X_F7] = 0x118, 707 [UNW_S390X_F8] = 0x120, 708 [UNW_S390X_F9] = 0x128, 709 [UNW_S390X_F10] = 0x130, 710 [UNW_S390X_F11] = 0x138, 711 [UNW_S390X_F12] = 0x140, 712 [UNW_S390X_F13] = 0x148, 713 [UNW_S390X_F14] = 0x150, 714 [UNW_S390X_F15] = 0x150, 715 [UNW_S390X_IP] = 0x08 716 #elif defined(UNW_TARGET_RISCV) 717 718 #if __riscv_xlen == 64 719 # define RISCV_REG_OFFSET(x) (8*x) 720 #elif __riscv_xlen == 32 721 # define RISCV_REG_OFFSET(x) (4*x) 722 #else 723 # error "Unsupported address size" 724 #endif 725 [UNW_RISCV_PC] = RISCV_REG_OFFSET(0), 726 [UNW_RISCV_X1] = RISCV_REG_OFFSET(1), 727 [UNW_RISCV_X2] = RISCV_REG_OFFSET(2), 728 [UNW_RISCV_X3] = RISCV_REG_OFFSET(3), 729 [UNW_RISCV_X4] = RISCV_REG_OFFSET(4), 730 [UNW_RISCV_X5] = RISCV_REG_OFFSET(5), 731 [UNW_RISCV_X6] = RISCV_REG_OFFSET(6), 732 [UNW_RISCV_X7] = RISCV_REG_OFFSET(7), 733 [UNW_RISCV_X8] = RISCV_REG_OFFSET(8), 734 [UNW_RISCV_X9] = RISCV_REG_OFFSET(9), 735 [UNW_RISCV_X10] = RISCV_REG_OFFSET(10), 736 [UNW_RISCV_X11] = RISCV_REG_OFFSET(11), 737 [UNW_RISCV_X12] = RISCV_REG_OFFSET(12), 738 [UNW_RISCV_X13] = RISCV_REG_OFFSET(13), 739 [UNW_RISCV_X14] = RISCV_REG_OFFSET(14), 740 [UNW_RISCV_X15] = RISCV_REG_OFFSET(15), 741 [UNW_RISCV_X16] = RISCV_REG_OFFSET(16), 742 [UNW_RISCV_X17] = RISCV_REG_OFFSET(17), 743 [UNW_RISCV_X18] = RISCV_REG_OFFSET(18), 744 [UNW_RISCV_X19] = RISCV_REG_OFFSET(19), 745 [UNW_RISCV_X20] = RISCV_REG_OFFSET(20), 746 [UNW_RISCV_X21] = RISCV_REG_OFFSET(21), 747 [UNW_RISCV_X22] = RISCV_REG_OFFSET(22), 748 [UNW_RISCV_X23] = RISCV_REG_OFFSET(23), 749 [UNW_RISCV_X24] = RISCV_REG_OFFSET(24), 750 [UNW_RISCV_X25] = RISCV_REG_OFFSET(25), 751 [UNW_RISCV_X26] = RISCV_REG_OFFSET(26), 752 [UNW_RISCV_X27] = RISCV_REG_OFFSET(27), 753 [UNW_RISCV_X28] = RISCV_REG_OFFSET(28), 754 [UNW_RISCV_X29] = RISCV_REG_OFFSET(29), 755 [UNW_RISCV_X30] = RISCV_REG_OFFSET(30), 756 [UNW_RISCV_X31] = RISCV_REG_OFFSET(31), 757 #else 758 # error Fix me. 759 #endif 760 }; 761