| /third_party/elfutils/tests/ |
| D | run-pt_gnu_prop-tests.sh | 53 01 [RO: .interp]
54 …02 [RO: .interp .note.gnu.build-id .note.gnu.property .note.ABI-tag .gnu.hash .dynsym .dynstr…
55 03 [RO: .init .plt .plt.sec .text .fini]
56 04 [RO: .rodata .eh_frame_hdr .eh_frame]
59 07 [RO: .note.gnu.build-id .note.gnu.property .note.ABI-tag]
60 08 [RO: .note.gnu.property]
61 09 [RO: .eh_frame_hdr]
104 01 [RO: .interp]
105 …02 [RO: .interp .note.gnu.property .note.gnu.build-id .note.ABI-tag .gnu.hash .dynsym .dynstr…
106 03 [RO: .init .text .fini]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 199 RegisterOperand RO> :
200 InstSE<(outs), (ins RO:$rs, opnd:$offset),
209 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
211 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
213 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
222 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
224 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
226 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
259 class LLBaseMM<string opstr, RegisterOperand RO> :
260 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
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| D | MipsInstrInfo.td | 1313 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1316 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1318 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1325 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1329 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1331 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1347 class LogicNOR<string opstr, RegisterOperand RO>:
1348 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1350 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1356 RegisterOperand RO, InstrItinClass itin,
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| D | MicroMipsDSPInstrInfo.td | 217 RegisterOperand RO, Operand ImmOpnd> {
218 dag OutOperandList = (outs RO:$rt);
219 dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
253 InstrItinClass itin, RegisterOperand RO> {
254 dag OutOperandList = (outs RO:$rd);
255 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
336 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
339 dag InOperandList = (ins RO:$ac);
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| D | MipsDSPInstrInfo.td | 335 RegisterOperand RO> {
336 dag OutOperandList = (outs RO:$rd);
339 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
345 InstrItinClass itin, RegisterOperand RO> {
346 dag OutOperandList = (outs RO:$rd);
347 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
349 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
356 RegisterOperand RO, Operand ImmOpnd> {
357 dag OutOperandList = (outs RO:$rd);
358 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
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| D | Mips64InstrInfo.td | 455 class Count1s<string opstr, RegisterOperand RO>:
456 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
457 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
461 class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO,
463 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1),
465 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))],
489 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
490 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
492 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
500 class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> :
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| /third_party/ffmpeg/libavfilter/ |
| D | f_perms.c | 74 enum perm { RO, RW }; enumerator
83 enum perm in_perm = av_frame_is_writable(frame) ? RW : RO; in filter_frame()
87 case MODE_TOGGLE: out_perm = in_perm == RO ? RW : RO; break; in filter_frame()
88 case MODE_RANDOM: out_perm = av_lfg_get(&s->lfg) & 1 ? RW : RO; break; in filter_frame()
89 case MODE_RO: out_perm = RO; break; in filter_frame()
98 if (in_perm == RO && out_perm == RW) { in filter_frame()
101 } else if (in_perm == RW && out_perm == RO) { in filter_frame()
109 if (in_perm == RW && out_perm == RO) in filter_frame()
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| /third_party/skia/third_party/externals/spirv-cross/shaders-no-opt/asm/comp/ |
| D | buffer-reference-aliased-block-name.nocompat.vk.asm.comp | 20 OpName %RO "Alias"
21 OpMemberName %RO 0 "v"
33 OpMemberDecorate %RO 0 NonWritable
34 OpMemberDecorate %RO 0 Offset 0
35 OpDecorate %RO Block
56 %RO = OpTypeStruct %_runtimearr_v4float
57 %_ptr_PhysicalStorageBuffer_RO = OpTypePointer PhysicalStorageBuffer %RO
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| /third_party/ltp/testcases/kernel/fs/fs_readonly/ |
| D | test_robind.sh | 143 local RO=$3
158 if [ "$RO" = "false" -a $tst_result -ne 0 -o "$RO" = "true" -a \
163 $dir $fs_type read-only flag: $RO"
166 $dir $fs_type read-only flag: $RO"
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| /third_party/typescript/tests/baselines/reference/ |
| D | unionTypeWithIndexSignature.types | 67 type RO = { foo: number } | { readonly [s: string]: string }
68 >RO : RO
72 declare var ro: RO
73 >ro : RO
78 >ro : RO
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| D | unionTypeWithIndexSignature.symbols | 57 type RO = { foo: number } | { readonly [s: string]: string }
58 >RO : Symbol(RO, Decl(unionTypeWithIndexSignature.ts, 10, 5))
62 declare var ro: RO
64 >RO : Symbol(RO, Decl(unionTypeWithIndexSignature.ts, 10, 5))
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| D | unionTypeWithIndexSignature.js | 13 type RO = { foo: number } | { readonly [s: string]: string }
14 declare var ro: RO
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| D | unionTypeWithIndexSignature.errors.txt | 26 type RO = { foo: number } | { readonly [s: string]: string }
27 declare var ro: RO
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| /third_party/skia/third_party/externals/spirv-cross/reference/opt/shaders/vulkan/comp/ |
| D | buffer-reference-decorations.nocompat.vk.comp.vk | 5 layout(buffer_reference) buffer RO;
8 layout(buffer_reference, std430) readonly buffer RO
25 RO ro;
|
| /third_party/skia/third_party/externals/spirv-cross/reference/shaders/vulkan/comp/ |
| D | buffer-reference-decorations.nocompat.vk.comp.vk | 5 layout(buffer_reference) buffer RO;
8 layout(buffer_reference, std430) readonly buffer RO
25 RO ro;
|
| /third_party/vk-gl-cts/external/vulkancts/modules/vulkan/image/ |
| D | vktImageDepthStencilDescriptorTests.cpp | 108 RO = 1, // Different subtypes, see below. enumerator
115 else if (access == AspectAccess::RO) stream << "ro"; in operator <<()
146 return ((aspect == VK_IMAGE_ASPECT_STENCIL_BIT) ? AspectAccess::RW : AspectAccess::RO); in getLegalAccess()
148 return ((aspect == VK_IMAGE_ASPECT_DEPTH_BIT) ? AspectAccess::RW : AspectAccess::RO); in getLegalAccess()
150 return ((aspect == VK_IMAGE_ASPECT_DEPTH_BIT) ? AspectAccess::RO : AspectAccess::NONE); in getLegalAccess()
152 return ((aspect == VK_IMAGE_ASPECT_STENCIL_BIT) ? AspectAccess::RO : AspectAccess::NONE); in getLegalAccess()
171 …hment = (depthAccess == AspectAccess::RW || (depthAccess == AspectAccess::RO && de::contains(begi… in incompatibleInputAttachmentAccess()
172 …nt = (stencilAccess == AspectAccess::RW || (stencilAccess == AspectAccess::RO && de::contains(begi… in incompatibleInputAttachmentAccess()
173 …const bool depthAsInputAttachment = (depthAccess == AspectAccess::RO && de::contains(begin(*depthR… in incompatibleInputAttachmentAccess()
174 …const bool stencilAsInputAttachment = (stencilAccess == AspectAccess::RO && de::contains(begin(*st… in incompatibleInputAttachmentAccess()
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| /third_party/ltp/tools/sparse/sparse-src/validation/ |
| D | enum-bitwise.c | 8 RO = (__force bits) 1, enumerator
13 _Static_assert([typeof(RO)] == [bits], "RO");
|
| /third_party/cmsis/CMSIS/Core/Include/ |
| D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /third_party/typescript/tests/cases/conformance/types/union/ |
| D | unionTypeWithIndexSignature.ts | 14 type RO = { foo: number } | { readonly [s: string]: string } alias
15 declare var ro: RO
|
| /third_party/skia/third_party/externals/spirv-cross/shaders/vulkan/comp/ |
| D | buffer-reference-decorations.nocompat.vk.comp | 5 layout(std430, buffer_reference) readonly buffer RO
22 RO ro;
|
| /third_party/openGLES/extensions/SUN/ |
| D | SUN_triangle_list.txt | 303 example REPLACE_OLDEST is abbreviated RO and REPLACE_MIDDLE is
314 V4 RO / \ / \ / Triangle Strip
315 V5 RO / \/ \/
316 V6 RO .-------.-------.
346 V24 RO | \ | \ | /\
347 V25 RO | \| 25/ \
348 V26 RO .-----.-----.---.28 Mixed Strip & Fan
349 V27 RO 21 23 /|\ |
354 V32 RO \ /
|
| /third_party/skia/third_party/externals/opengl-registry/extensions/SUN/ |
| D | SUN_triangle_list.txt | 303 example REPLACE_OLDEST is abbreviated RO and REPLACE_MIDDLE is
314 V4 RO / \ / \ / Triangle Strip
315 V5 RO / \/ \/
316 V6 RO .-------.-------.
346 V24 RO | \ | \ | /\
347 V25 RO | \| 25/ \
348 V26 RO .-----.-----.---.28 Mixed Strip & Fan
349 V27 RO 21 23 /|\ |
354 V32 RO \ /
|
| /third_party/python/Lib/test/ |
| D | test_enum.py | 2227 RO = 0 variable in TestFlag.Open
2256 self.assertEqual(str(Open.RO), 'Open.RO')
2259 self.assertEqual(str(Open.RO | Open.CE), 'Open.CE')
2261 self.assertEqual(str(~Open.RO), 'Open.CE|AC|RW|WO')
2264 self.assertEqual(str(~(Open.RO | Open.CE)), 'Open.AC')
2283 self.assertEqual(repr(Open.RO), '<Open.RO: 0>')
2286 self.assertEqual(repr(Open.RO | Open.CE), '<Open.CE: 524288>')
2288 self.assertEqual(repr(~Open.RO), '<Open.CE|AC|RW|WO: 524291>')
2291 self.assertEqual(repr(~(Open.RO | Open.CE)), '<Open.AC: 3>')
2309 self.assertIs(Open.RO | Open.CE, Open.CE)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 820 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); in updatePhiNodes() local
822 SR = RO.getReg(), SSR = RO.getSubReg(); in updatePhiNodes()
824 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes()
826 FR = RO.getReg(), FSR = RO.getSubReg(); in updatePhiNodes()
|
| /third_party/libphonenumber/resources/geocoding/en/ |
| D | 55.txt | 8827 55692101|Vilhena - RO
8828 55692181|Porto Velho - RO
8829 55692183|Ji-Paraná - RO
8830 55693025|Porto Velho - RO
8831 55693026|Porto Velho - RO
8832 55693043|Porto Velho - RO
8833 55693216|Porto Velho - RO
8834 55693218|Porto Velho - RO
8835 55693222|Porto Velho - RO
8836 55693230|Candeias do Jamari - RO
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