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Searched refs:SETULT (Results 1 – 25 of 47) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h1061 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1087 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAnalysis.cpp215 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
227 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
247 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp3061 case ISD::SETULT: { in get32BitZExtCompare()
3234 case ISD::SETULT: { in get32BitSExtCompare()
3390 case ISD::SETULT: { in get64BitZExtCompare()
3553 case ISD::SETULT: { in get64BitSExtCompare()
3802 case ISD::SETULT: in SelectCC()
3829 case ISD::SETULT: in SelectCC()
3885 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
3917 case ISD::SETULT: return 0; in getCRIdxForSetCC()
3938 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
3946 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
DPPCInstrQPX.td1010 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULT),
1057 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULT),
1116 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULT)),
1137 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULT)),
1158 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULT)),
DPPCInstrInfo.td3384 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3447 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3627 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3655 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3667 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3695 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3933 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3964 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3985 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
4007 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
DPPCInstrSPE.td850 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
871 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp488 case ISD::SETULT: in NegateCC()
694 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
DBPFInstrInfo.td101 [{return (N->getZExtValue() == ISD::SETULT);}]>;
121 [{return (N->getZExtValue() == ISD::SETULT);}]>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp136 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
142 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
821 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
822 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
859 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
860 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
DSIInsertSkips.cpp234 case ISD::SETULT: in kill()
DAMDGPUInstructions.td261 def COND_ULT : PatFrag<(ops), (OtherVT SETULT)>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp1382 case ISD::SETULT: in PromoteSetCCOperands()
2145 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
2215 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
2345 ISD::SETULT); in ExpandIntRes_ADDSUB()
2357 ISD::SETULT); in ExpandIntRes_ADDSUB()
2366 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2439 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
3193 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
3846 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
3916 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
DTargetLowering.cpp371 case ISD::SETULT: in softenSetCCOperands()
2939 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
3189 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
3193 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
3374 case ISD::SETULT: in SimplifySetCC()
3397 case ISD::SETULT: in SimplifySetCC()
3599 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
3611 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
3667 if (Cond == ISD::SETULT && in SimplifySetCC()
3733 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
[all …]
DSelectionDAGDumper.cpp420 case ISD::SETULT: return "setult"; in getOperationName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCISelLowering.cpp49 case ISD::SETULT: in ISDCCtoARCCC()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRISelLowering.cpp436 case ISD::SETULT: in intCCToAVRCC()
530 CC = ISD::SETULT; in getAVRCmp()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp960 case ISD::SETULT: in isLegalDSPCondCode()
1767 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1773 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1856 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
DMipsMSAInstrInfo.td150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
DMipsDSPInstrInfo.td1428 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1441 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc16569 /* 30752*/ OPC_CheckChild2CondCode, ISD::SETULT,
16574 …Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETULT:{ *:[Other] }) - C…
16585 /* 30782*/ OPC_CheckChild2CondCode, ISD::SETULT,
16590 …Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETULT:{ *:[Other] }) - C…
16645 /* 30916*/ OPC_CheckChild2CondCode, ISD::SETULT,
16650 …Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETULT:{ *:[Other] }) - C…
16662 /* 30947*/ OPC_CheckChild2CondCode, ISD::SETULT,
16667 …(setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) - C…
16694 /* 31007*/ OPC_CheckChild2CondCode, ISD::SETULT,
16699 …(setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) - C…
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td695 def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">;
1297 (setcc node:$lhs, node:$rhs, SETULT)>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp160 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, in RISCVTargetLowering()
376 case ISD::SETULT: in getBranchOpcodeForIntCondCode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp828 case ISD::SETULT: in IntCondCCodeToICC()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp1843 case ISD::SETULT: return ARMCC::LO; in IntCCToARMCC()
1869 case ISD::SETULT: CondCode = ARMCC::LT; break; in FPCCToARMCC()
4231 case ISD::SETULT: in getARMCmp()
4234 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
4248 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
4657 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT) in checkVSELConstraints()
4663 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT) in checkVSELConstraints()
4674 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || in checkVSELConstraints()
6289 case ISD::SETULT: Invert = true; Opc = ARMCC::GE; break; in LowerVSETCC()
6330 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH; in LowerVSETCC()
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