| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 35 SHL = 0x17, enumerator
92 case SHL: in lanaiAluCodeToString()
112 .Case("sh", SHL) in stringToLanaiAluCode()
134 case ISD::SHL: in isdToLanaiAluCode()
135 return AluCode::SHL; in isdToLanaiAluCode()
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| D | LanaiISelLowering.cpp | 946 Res = DAG.getNode(ISD::SHL, DL, VT, V, in LowerMUL()
960 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32)); in LowerMUL()
1264 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerSHL_PARTS()
1268 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerSHL_PARTS()
1276 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerSHL_PARTS()
1315 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32); in LowerSRL_PARTS()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. in getArithmeticInstrCost()
451 { ISD::SHL, MVT::v16i16, 1 }, // psllw. in getArithmeticInstrCost()
466 { ISD::SHL, MVT::v8i16, 1 }, // psllw. in getArithmeticInstrCost()
467 { ISD::SHL, MVT::v4i32, 1 }, // pslld in getArithmeticInstrCost()
468 { ISD::SHL, MVT::v2i64, 1 }, // psllq. in getArithmeticInstrCost()
498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw in getArithmeticInstrCost()
502 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw in getArithmeticInstrCost()
[all …]
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| D | X86ISelDAGToDAG.cpp | 676 if (U->getOperand(0).getOpcode() == ISD::SHL && in IsProfitableToFold()
680 if (U->getOperand(1).getOpcode() == ISD::SHL && in IsProfitableToFold()
702 case ISD::SHL: in IsProfitableToFold()
855 case ISD::SHL: in PreprocessISelDAG()
866 case ISD::SHL: NewOpc = X86ISD::VSHLV; break; in PreprocessISelDAG()
1652 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount); in foldMaskAndShiftToExtract()
1695 if (Shift.getOpcode() != ISD::SHL || in foldMaskedShiftToScaledMask()
1722 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in foldMaskedShiftToScaledMask()
1832 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt); in foldMaskAndShiftToScale()
1889 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewAnd, NewSHLAmt); in foldMaskedShiftToBEXTR()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 603 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL) in SelectSHL()
884 case ISD::SHL: return SelectSHL(N); in Select()
1046 if (T1.getOpcode() != ISD::SHL) in ppAddrReorderAddShl()
1071 SDValue NewShl = DAG.getNode(ISD::SHL, DL, VT, NewAdd, C); in ppAddrReorderAddShl()
1147 SDValue NewShl = DAG.getNode(ISD::SHL, dl, VT, NewSrl, DC); in ppAddrRewriteAndSrl()
1616 case ISD::SHL: in isOpcodeHandled()
1743 if (Val.getOpcode() != ISD::SHL || in findSHL()
1810 if (Val.getOpcode() == ISD::SHL) { in getPowerOf2Factor()
1829 } else if (V.getOpcode() == ISD::SHL) { in willShiftRightEliminate()
1850 } else if (V.getOpcode() == ISD::SHL) { in factorOutPowerOf2()
[all …]
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| /third_party/openssl/crypto/bn/asm/ |
| D | ppc.pl | 126 $SHL= "slw"; # shift left
150 $SHL= "sld"; # shift left
1662 $SHL r3,r3,r7 # h = (h<< i)
1664 $SHL r5,r5,r7 # d<<=i
1666 $SHL r4,r4,r7 # l <<=i
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| D | bn-c64xplus.asm | 195 [!A2] SHL A6,A0,A6 ; normalize dv
199 ||[!A2] SHL A4,1,A5:A4 ; lo<<1
208 || SHL A4,1,A5:A4 ; lo<<1
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| /third_party/flutter/skia/src/sksl/ |
| D | SkSLLexer.h | 138 #undef SHL
139 SHL, enumerator
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| D | SkSLUtil.cpp | 64 case Token::SHLEQ: return Token::SHL; in remove_assignment()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4_gs_visitor.cpp | 363 inst = emit(SHL(dst_reg(channel_mask), one, channel)); in emit_control_data_bits()
407 emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u))); in set_stream_control_data_bits()
415 emit(SHL(dst_reg(mask), sid, shift_count)); in set_stream_control_data_bits()
560 emit(SHL(dst_reg(mask), one, prev_count)); in gs_end_primitive()
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| D | brw_fs_nir.cpp | 1875 bld.SHL(result, op[0], op[1]); in nir_emit_alu()
2197 bld.SHL(result, one, x); in intexp2()
2334 fwa_bld.SHL(channel_mask, channel_mask, brw_imm_ud(16u)); in emit_gs_control_data_bits()
2399 abld.SHL(shift_count, vertex_count, brw_imm_ud(1u)); in set_gs_stream_control_data_bits()
2407 abld.SHL(mask, sid, shift_count); in set_gs_stream_control_data_bits()
2564 bld.SHL(channel_offsets, sequence, brw_imm_ud(2u)); in emit_gs_input_load()
2566 bld.SHL(vertex_offset_bytes, in emit_gs_input_load()
2597 bld.SHL(icp_offset_bytes, in emit_gs_input_load()
2756 bld.SHL(vertex_offset_bytes, in get_tcs_single_patch_icp_handle()
2805 bld.SHL(channel_offsets, sequence, brw_imm_ud(2u)); in get_tcs_eight_patch_icp_handle()
[all …]
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| D | brw_mesh.cpp | 989 bld8.SHL(mask, one, mask); in emit_urb_indirect_writes()
990 bld8.SHL(mask, mask, brw_imm_ud(16)); in emit_urb_indirect_writes()
1077 ubld8.SHL(seq_ud, seq_ud, brw_imm_ud(2)); in emit_urb_indirect_reads()
1097 bld8.SHL(comp, comp, brw_imm_ud(ffs(REG_SIZE) - 1)); in emit_urb_indirect_reads()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 86 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; in PromoteIntegerResult()
711 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
713 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
772 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, in PromoteIntRes_MULFIX()
949 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SHL()
1211 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, in PromoteIntRes_VAARG()
1290 case ISD::SHL: in PromoteIntegerOperand()
1446 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, in PromoteIntOp_BUILD_PAIR()
1895 case ISD::SHL: in ExpandIntegerResult()
1971 if (N->getOpcode() == ISD::SHL) { in ExpandShiftByConstant()
[all …]
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| D | LegalizeVectorOps.cpp | 385 case ISD::SHL: in LegalizeOp()
799 DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
818 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); in ExpandLoad()
1058 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) in ExpandSEXTINREG()
1068 SDValue Op = DAG.getNode(ISD::SHL, DL, VT, Node->getOperand(0), ShiftSz); in ExpandSEXTINREG()
1127 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1221 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) && in ExpandBITREVERSE()
1238 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBITREVERSE()
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| D | DAGCombiner.cpp | 1539 case ISD::SHL: return visitSHL(N); in visit()
1661 case ISD::SHL: in combine()
2432 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLikeCommutative()
2435 DAG.getNode(ISD::SHL, DL, VT, in visitADDLikeCommutative()
3502 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc); in visitMUL()
3512 DAG.getNode(ISD::SHL, DL, VT, N0, in visitMUL()
3542 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT)); in visitMUL()
3551 if (N0.getOpcode() == ISD::SHL && in visitMUL()
3554 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1)); in visitMUL()
3565 if (N0.getOpcode() == ISD::SHL && in visitMUL()
[all …]
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| D | LegalizeDAG.cpp | 809 ISD::SHL, dl, Hi.getValueType(), Hi, in LegalizeLoadOps()
838 ISD::SHL, dl, Hi.getValueType(), Hi, in LegalizeLoadOps()
1177 case ISD::SHL: in LegalizeOp()
1552 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
2626 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT)); in ExpandBITREVERSE()
2633 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT)); in ExpandBITREVERSE()
2640 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT)); in ExpandBITREVERSE()
2649 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT)); in ExpandBITREVERSE()
2674 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in ExpandBSWAP()
2675 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in ExpandBSWAP()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 172 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, in addIPMSequence() local
174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
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| D | ARMISelLowering.cpp | 191 setOperationAction(ISD::SHL, VT, Custom); in addTypeForNEON()
262 setOperationAction(ISD::SHL, VT, Custom); in addMVEVectorTypes()
918 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
1080 setOperationAction(ISD::SHL, MVT::i64, Custom); in ARMTargetLowering()
1458 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
1814 if (Op.getOpcode() != ISD::SHL) in isSHL16()
3192 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex, in LowerGlobalTLSAddressWindows()
3675 SDValue SHL = in LowerINTRINSIC_WO_CHAIN() local
3676 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy)); in LowerINTRINSIC_WO_CHAIN()
3678 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy)); in LowerINTRINSIC_WO_CHAIN()
[all …]
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| /third_party/flutter/skia/src/sksl/lex/ |
| D | sksl.lex | 60 SHL = "<<"
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| /third_party/skia/src/sksl/lex/ |
| D | sksl.lex | 64 SHL = "<<"
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 814 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
816 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
818 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
849 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
850 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1289 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1293 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
[all …]
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| /third_party/openssl/crypto/sha/asm/ |
| D | sha512-ppc.pl | 54 $SHL="sldi";
62 $SHL="slwi";
203 $SHL $num,$num,`log(16*$SZ)/log(2)`
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.h | 207 A_ALU2(SHL)
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 112 OP12(SHL)
|